1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
|
.\" $NetBSD: OPENSSL_ppccap.3,v 1.2 2026/04/08 17:06:45 christos Exp $
.\"
.\" -*- mode: troff; coding: utf-8 -*-
.\" Automatically generated by Pod::Man v6.0.2 (Pod::Simple 3.45)
.\"
.\" Standard preamble:
.\" ========================================================================
.de Sp \" Vertical space (when we can't use .PP)
.if t .sp .5v
.if n .sp
..
.de Vb \" Begin verbatim text
.ft CW
.nf
.ne \\$1
..
.de Ve \" End verbatim text
.ft R
.fi
..
.\" \*(C` and \*(C' are quotes in nroff, nothing in troff, for use with C<>.
.ie n \{\
. ds C` ""
. ds C' ""
'br\}
.el\{\
. ds C`
. ds C'
'br\}
.\"
.\" Escape single quotes in literal strings from groff's Unicode transform.
.ie \n(.g .ds Aq \(aq
.el .ds Aq '
.\"
.\" If the F register is >0, we'll generate index entries on stderr for
.\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index
.\" entries marked with X<> in POD. Of course, you'll have to process the
.\" output yourself in some meaningful fashion.
.\"
.\" Avoid warning from groff about undefined register 'F'.
.de IX
..
.nr rF 0
.if \n(.g .if rF .nr rF 1
.if (\n(rF:(\n(.g==0)) \{\
. if \nF \{\
. de IX
. tm Index:\\$1\t\\n%\t"\\$2"
..
. if !\nF==2 \{\
. nr % 0
. nr F 2
. \}
. \}
.\}
.rr rF
.\"
.\" Required to disable full justification in groff 1.23.0.
.if n .ds AD l
.\" ========================================================================
.\"
.IX Title "OPENSSL_ppccap 3"
.TH OPENSSL_ppccap 3 2026-04-07 3.5.6 OpenSSL
.\" For nroff, turn off justification. Always turn off hyphenation; it makes
.\" way too many mistakes in technical documents.
.if n .ad l
.nh
.SH NAME
OPENSSL_ppccap \- the PowerPC processor capabilities vector
.SH SYNOPSIS
.IX Header "SYNOPSIS"
.Vb 1
\& env OPENSSL_ppccap=... <application>
.Ve
.SH DESCRIPTION
.IX Header "DESCRIPTION"
libcrypto supports PowerPC instruction set extensions. These extensions are
represented by bits in the PowerPC capabilities vector. When libcrypto
initializes, it stores the results returned by PowerPC CPU capabilities detection
logic in the PowerPC capabilities vector. The CPU capabilities detection methods
are OS\-dependent and use a combination of information gathered by the kernel
during boot and probe functions that attempt to execute instructions and trap
illegal instruction signals with a signal handler.
.PP
To override the set of extensions available to an application, you can set the
\&\fBOPENSSL_ppccap\fR environment variable before you start the application. The
environment variable is assigned a numerical value that denotes the bits in
the PowerPC capabilities vector. The ppc_arch.h header file states that, "Flags\*(Aq
usage can appear ambiguous, because they are set rather to reflect OpenSSL
performance preferences than actual processor capabilities."
.PP
Multiple extensions are enabled by logically OR\-ing the values that represent the
desired extensions.
.PP
\&\fBNotes\fR: Enabling an extension on a CPU that does not support the extension
will result in a SIGILL crash. On AIX, all vector instructions can be disabled
with the schedo \-ro allow_vmx=0 command. DO NOT USE THIS COMMAND to disable
vector instructions in the OS when it is running on a CPU level that supports the
instructions without also disabling them in libcrpto via the OPENSSL_ppccap
environment variable or the application will crash with a SIGILL.
.PP
Currently, the following extensions are defined:
.IP 0x01 4
.IX Item "0x01"
Name: \fBPPC_FPU64\fR
.Sp
This flag is obsolete.
.IP 0x02 4
.IX Item "0x02"
Name: \fBPPC_ALTIVEC\fR
.Sp
Meaning: Use AltiVec (aka VMX) instructions. In some but not all cases, this
capability gates the use of later ISA vector instructions. The associated probe
instruction is vor (vector logical or).
.Sp
Effect: Enables use of vector instructions but does not enable extensions added
at specific ISA levels. However, disabling this capability disables a subset of
vector extensions added at specific ISA levels even if they are otherwise
enabled.
.IP 0x04 4
.IX Item "0x04"
Name: \fBPPC_CRYPTO207\fR
.Sp
Meaning: Use instructions added in ISA level 2.07. The associated probe
instruction instruction is vcipher (vector AES cipher round).
.Sp
Effect: Enables AES, SHA\-2 sigma, and other ISA 2.07 instructions for AES, SHA\-2,
GHASH, and Poly1305.
.IP 0x08 4
.IX Item "0x08"
Name: \fBPPC_FPU\fR
.Sp
Meaning: Use FPU instructions. The associated probe instruction is fmr (floating
move register).
.Sp
Effect: Enables Poly1305 FPU implementation. The PPC_CRYPTO207 capability
overrides this effect.
.IP 0x10 4
.IX Item "0x10"
Name: \fBPPC_MADD300\fR
.Sp
Meaning: Use instructions added in ISA level 3.00. The associated probe
instruction is maddhdu (multiply\-add high doubleword unsigned).
.Sp
Effect: Enables use of the polynomial multiply and other ISA 3.00 instructions
for AES\-GCM, P\-384, and P\-521.
.IP 0x20 4
.IX Item "0x20"
Name: \fBPPC_MFTB\fR
.Sp
Meaning: Use the mftb (move from time base) instruction. The associated probe
instruction is mftb.
.Sp
Effect: Enables use of the mftb instruction to sample the lower 32 bits of the
CPU time base register in order to acquire entropy. Considered obsolete. The
PPC_MFSPR268 capability overrides this capability.
.IP 0x40 4
.IX Item "0x40"
Name: \fBPPC_MFSPR268\fR
.Sp
Meaning: Use the mfspr (move from special purpose register) instruction to
read SPR 268. The associated probe instruction is mfspr 268.
.Sp
Effect: Enables use of the mfspr instruction to sample the lower 32 bits of the
CPU time base register from SPR 268, the TBL (time base lower) register, in order
to acquire entropy.
.IP 0x80 4
.IX Item "0x80"
Name: \fBPPC_BRD31\fR
.Sp
Meaning: Use instructions added in ISA level 3.1. The associated probe instruction
is brd (byte\-reverse doubleword).
.Sp
Effect: Enables use of ISA 3.1 instructions in ChaCha20.
.SH "RETURN VALUES"
.IX Header "RETURN VALUES"
Not available.
.SH EXAMPLES
.IX Header "EXAMPLES"
Check currently detected capabilities:
.PP
.Vb 2
\& $ openssl info \-cpusettings
\& OPENSSL_ppccap=0x2E
.Ve
.PP
The detected capabilities in the above example indicate that PPC_MFTB, PPC_FPU,
PPC_CRYPTO207, PPC_MFSPR268, and PPC_ALTIVEC are enabled.
.PP
Disable all instruction set extensions:
.PP
.Vb 1
\& OPENSSL_ppccap=0x00
.Ve
.PP
Enable base AltiVec extensions:
.PP
.Vb 1
\& OPENSSL_ppccap=0x02
.Ve
.SH COPYRIGHT
.IX Header "COPYRIGHT"
Copyright 2025 The OpenSSL Project Authors. All Rights Reserved.
.PP
Licensed under the Apache License 2.0 (the "License"). You may not use
this file except in compliance with the License. You can obtain a copy
in the file LICENSE in the source distribution or at
<https://www.openssl.org/source/license.html>.
|
