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<table class="head">
<tr>
<td class="head-ltitle">MCA(4)</td>
<td class="head-vol">Device Drivers Manual (amd64)</td>
<td class="head-rtitle">MCA(4)</td>
</tr>
</table>
<div class="manual-text">
<section class="Sh">
<h1 class="Sh" id="NAME"><a class="permalink" href="#NAME">NAME</a></h1>
<p class="Pp"><code class="Nm">mca</code> — <span class="Nd">Machine
Check Architecture</span></p>
</section>
<section class="Sh">
<h1 class="Sh" id="DESCRIPTION"><a class="permalink" href="#DESCRIPTION">DESCRIPTION</a></h1>
<p class="Pp">The <code class="Nm">mca</code> subsystem provides support for the
x86 Machine Check Architecture. The CPU uses this architecture to report
various hardware problems, ranging from correctible errors to uncorrectible
fatal errors. The <code class="Nm">mca</code> subsystem processes the errors
reported by the CPU and logs them according to the user-supplied
configuration.</p>
<p class="Pp">The <code class="Nm">mca</code> subsystem is automatically
compiled into every x86 kernel.</p>
</section>
<section class="Sh">
<h1 class="Sh" id="LOGGING"><a class="permalink" href="#LOGGING">LOGGING</a></h1>
<p class="Pp">By default, every message is logged to four locations:</p>
<ul class="Bl-bullet">
<li>The console</li>
<li>The system log (using the <code class="Dv">LOG_KERN</code>
<a class="Xr">syslog(3)</a> facility)</li>
<li>An in-kernel cache of event records</li>
<li>A statistics array</li>
</ul>
<p class="Pp">An administrator can disable console logging of non-fatal errors
using the <var class="Va">hw.mca.uselog</var> <a class="Xr">sysctl(8)</a> or
tunable setting. Fatal errors are always logged to the console.</p>
<p class="Pp">The in-kernel cache of event records can be accessed from
userspace using the <var class="Va">hw.mca.records</var>
<a class="Xr">sysctl(8)</a> node. By default, the in-kernel cache of event
records grows without bound and contains records for all
<code class="Nm">mca</code> events received since system boot. The cache can
be limited (in which case it turns into a ring buffer) or disabled
altogether using the <var class="Va">hw.mca.maxcount</var>
<a class="Xr">sysctl(8)</a> or tunable setting.</p>
<p class="Pp">The statistics array can be retrieved using the
<var class="Va">hw.mca.stats</var> <a class="Xr">sysctl(8)</a> node.</p>
</section>
<section class="Sh">
<h1 class="Sh" id="SYSCTL_VARIABLES"><a class="permalink" href="#SYSCTL_VARIABLES">SYSCTL
VARIABLES</a></h1>
<p class="Pp">The subsystem has a number of configuration options to control the
way events are processed and logged. These options are configured via
<a class="Xr">sysctl(8)</a> variables or tunables. These settings control
things such as log destination, event limiting, and sampling. These settings
directly impact both the completeness of logs and the performance impact of
processing <code class="Nm">mca</code> events. A system administrator may
want to review these and modify them to obtain the appropriate behavior in
their environment.</p>
<dl class="Bl-tag">
<dt id="hw.mca.enabled"><var class="Va">hw.mca.enabled</var></dt>
<dd>(Only settable as a tunable.)
<p class="Pp">If set to 0, the CPU is not configured to send
<code class="Nm">mca</code> messages to the kernel.</p>
<p class="Pp">Default is 1 (enabled).</p>
</dd>
<dt id="hw.mca.log_corrected"><var class="Va">hw.mca.log_corrected</var></dt>
<dd>(Settable as a tunable or sysctl.)
<p class="Pp">If enabled, corrected messages are logged to console, syslog,
the in-kernel event cache, and the statistics array (subject to separate
configuration controlling those facilities). If disabled, corrected
messages are only logged to the in-kernel event cache (subject to
separate configuration controlling that facility).</p>
<p class="Pp">Default is 1 (enabled).</p>
</dd>
<dt id="hw.mca.intel6h_HSD131"><var class="Va">hw.mca.intel6h_HSD131</var></dt>
<dd>(Only settable as a tunable.)
<p class="Pp">This setting enables a workaround for benign corrected parity
errors which may be reported by certain Intel desktop Haswell CPUs. (The
name "HSD131" comes from the name of the Intel erratum report
about this issue.)</p>
<p class="Pp">Default is 0 (disabled).</p>
</dd>
<dt id="hw.mca.amd10h_L1TP"><var class="Va">hw.mca.amd10h_L1TP</var></dt>
<dd>(Only settable as a tunable.)
<p class="Pp">Enable logging of level one TLB parity errors on certain AMD
CPUs. This option has no impact on other CPUs.</p>
<p class="Pp">Default is 1 (enabled).</p>
</dd>
<dt id="hw.mca.erratum383"><var class="Va">hw.mca.erratum383</var></dt>
<dd>(Only settable as a tunable.)
<p class="Pp">This setting enables a workaround for Erratum 383 on AMD
Family 10h CPUs. The erratum changes the way pages are promoted to or
demoted from being super-pages. On affected AMD CPUs, either
<var class="Va">hw.mca.amd10h_L1TP</var> or
<var class="Va">hw.mca.erratum383</var> must be on. If both are off, the
system will dynamically enable <var class="Va">hw.mca.erratum383</var>
at boot time.</p>
<p class="Pp">Default is 0 (disabled).</p>
</dd>
<dt id="hw.mca.uselog"><var class="Va">hw.mca.uselog</var></dt>
<dd>(Settable as a tunable or sysctl.)
<p class="Pp">If enabled, the system will send messages about non-fatal
<code class="Nm">mca</code> events to syslog and not to the console. If
disabled, the system will send messages about non-fatal
<code class="Nm">mca</code> events to both syslog and the console. Fatal
events are always logged to the console.</p>
<p class="Pp">Default is false (disabled).</p>
</dd>
<dt id="hw.mca.stats"><var class="Va">hw.mca.stats</var></dt>
<dd>(Read-only sysctl.)
<p class="Pp">This returns an array of <var class="Va">MCA_T_COUNT</var>
uint64_t values. The <var class="Vt">enum mca_stat_types</var>
definition in
<code class="In"><<a class="In">x86/mca.h</a>></code> provides the
value of <var class="Va">MCA_T_COUNT</var> and the index values for
various event types.</p>
</dd>
<dt id="hw.mca.log_interval"><var class="Va">hw.mca.log_interval</var></dt>
<dd>(Settable as a tunable or sysctl.)
<p class="Pp">This sets the minimum time (in seconds) between logging
correctible errors. The rate limit is only applied after the system
records a reasonable number of errors of the same type. The goal is to
reduce the impact of the system seeing and attempting to log a burst of
similar errors, which can be expensive (especially when printed to the
console). If this setting is 0, no rate limit is applied.</p>
<p class="Pp">Default is 0 (no rate limit).</p>
</dd>
<dt id="hw.mca.cmc_throttle"><var class="Va">hw.mca.cmc_throttle</var></dt>
<dd>(Settable as a tunable or sysctl. Only available if
<a class="Xr">apic(4)</a> support is enabled and the hardware supports CMC
interrupt throttling.)
<p class="Pp">This sets the maximum time (in seconds) to throttle CMC
interrupts. In normal operation, the system attempts to receive CMC
interrupts as soon as an event occurs. However, if a high rate of events
occurs in a short time, the system will begin throttling the CMC
interrupts. While the events continue to occur at a high rate, the
system will gradually increase the throttling interval until it reaches
the <var class="Va">hw.mca.cmc_throttle</var> setting.</p>
<p class="Pp">Default is 60 seconds.</p>
</dd>
<dt id="hw.mca.count"><var class="Va">hw.mca.count</var></dt>
<dd>(Read-only sysctl.)
<p class="Pp">This returns the current number of <code class="Nm">mca</code>
records in the in-kernel cache. This can be used to determine how many
records are available to read with the
<var class="Va">hw.mca.records</var> <a class="Xr">sysctl(8)</a>
interface. It can also be used to monitor the amount of memory used by
the in-kernel record cache.</p>
</dd>
<dt id="hw.mca.maxcount"><var class="Va">hw.mca.maxcount</var></dt>
<dd>(Settable as a tunable or sysctl.)
<p class="Pp">This setting controls the size and behavior of the in-kernel
cache of <code class="Nm">mca</code> records. If the setting is -1, the
in-kernel cache grows without bounds and contains a complete record
events since boot or the last time the
<var class="Va">hw.mca.maxcount</var> setting was changed. If the
setting is 0, the in-kernel cache is disabled. If the setting is a
positive integer, the in-kernel cache functions as a ring buffer with
the number of entries defined by the setting.</p>
<p class="Pp">Default is -1 (unlimited).</p>
</dd>
<dt id="hw.mca.interval"><var class="Va">hw.mca.interval</var></dt>
<dd>(Settable as a tunable or sysctl.)
<p class="Pp">This setting controls how often (in seconds) the kernel should
proactively scan for new <code class="Nm">mca</code> events. In many
circumstances, the CPU will send an interrupt to signal new events.
However, there are cases where the periodic scan for events will
discover new events.</p>
<p class="Pp">Default is 300 seconds.</p>
</dd>
<dt id="hw.mca.force_scan"><var class="Va">hw.mca.force_scan</var></dt>
<dd>(Settable only as a sysctl.)
<p class="Pp">Setting this to any non-zero value will force an immediate
scan for <code class="Nm">mca</code> events. Setting this to zero has no
effect. This is functionally a write-only setting. The current value is
always 0, even when a scan is running.</p>
<p class="Pp">Default is 0 (no scan requested).</p>
</dd>
<dt id="hw.mca.records.n"><var class="Va">hw.mca.records.n</var></dt>
<dd>(Read-only sysctl.)
<p class="Pp">This is used to copy <code class="Nm">mca</code> records from
the in-kernel cache to a user space process. The <var class="Va">n</var>
value in the <a class="Xr">sysctl(8)</a> node is an integer index into
the in-kernel cache. (Or, put differently, the "new" value
describes how many records the kernel should skip to find the desired
record.) The return value is a <var class="Vt">struct mca_record</var>,
which is defined in
<code class="In"><<a class="In">x86/mca.h</a>></code>.</p>
</dd>
</dl>
</section>
<section class="Sh">
<h1 class="Sh" id="LOADER_TUNABLES"><a class="permalink" href="#LOADER_TUNABLES">LOADER
TUNABLES</a></h1>
<p class="Pp">Tunables can be set at the <a class="Xr">loader(8)</a> prompt
before booting the kernel or stored in
<span class="Pa">/boot/loader.conf</span>. The tunables all have
corresponding <a class="Xr">sysctl(8)</a> entries. The tunables are listed
above in the <a class="Sx" href="#SYSCTL_VARIABLES">SYSCTL VARIABLES</a>
section.</p>
</section>
<section class="Sh">
<h1 class="Sh" id="COMPATIBILITY"><a class="permalink" href="#COMPATIBILITY">COMPATIBILITY</a></h1>
<p class="Pp"><code class="Nm">mca</code> is only available on x86 systems.</p>
</section>
<section class="Sh">
<h1 class="Sh" id="SEE_ALSO"><a class="permalink" href="#SEE_ALSO">SEE
ALSO</a></h1>
<p class="Pp"><a class="Xr">loader.conf(5)</a>, <a class="Xr">sysctl(8)</a>,
<a class="Xr">syslogd(8)</a></p>
</section>
<section class="Sh">
<h1 class="Sh" id="AUTHORS"><a class="permalink" href="#AUTHORS">AUTHORS</a></h1>
<p class="Pp">The <code class="Nm">mca</code> subsystem was originally written
by <span class="An">John Baldwin</span>
<<a class="Mt" href="mailto:jhb@FreeBSD.org">jhb@FreeBSD.org</a>>.</p>
<p class="Pp">This manual page was written by
<br/>
<span class="An">Jonathan Looney</span>
<<a class="Mt" href="mailto:jtl@FreeBSD.org">jtl@FreeBSD.org</a>>.</p>
</section>
</div>
<table class="foot">
<tr>
<td class="foot-date">January 14, 2026</td>
<td class="foot-os">FreeBSD 15.0</td>
</tr>
</table>
|
