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<table class="head">
<tr>
<td class="head-ltitle">DEVCFG(4)</td>
<td class="head-vol">Device Drivers Manual (arm)</td>
<td class="head-rtitle">DEVCFG(4)</td>
</tr>
</table>
<div class="manual-text">
<section class="Sh">
<h1 class="Sh" id="NAME"><a class="permalink" href="#NAME">NAME</a></h1>
<p class="Pp"><code class="Nm">devcfg</code> — <span class="Nd">Zynq PL
device config interface</span></p>
</section>
<section class="Sh">
<h1 class="Sh" id="SYNOPSIS"><a class="permalink" href="#SYNOPSIS">SYNOPSIS</a></h1>
<p class="Pp"><code class="Cd">device devcfg</code></p>
</section>
<section class="Sh">
<h1 class="Sh" id="DESCRIPTION"><a class="permalink" href="#DESCRIPTION">DESCRIPTION</a></h1>
<p class="Pp">The special file <span class="Pa">/dev/devcfg</span> can be used
to configure the PL (FPGA) section of the Xilinx Zynq-7000.</p>
<p class="Pp">On the first write to the character device at file offset 0, the
<code class="Nm">devcfg</code> driver asserts the top-level PL reset
signals, disables the PS-PL level shifters, and clears the PL configuration.
Write data is sent to the PCAP (processor configuration access port). When
the PL asserts the DONE signal, the devcfg driver will enable the level
shifters and release the top-level PL reset signals.</p>
<p class="Pp">The PL (FPGA) can be configured by writing the bitstream to the
character device like this:</p>
<div class="Bd Pp Bd-indent Li">
<pre>cat design.bit.bin > /dev/devcfg</pre>
</div>
<p class="Pp">The file should not be confused with the .bit file output by the
FPGA design tools. It is the binary form of the configuration bitstream. The
Xilinx <code class="Ic">promgen</code> tool can do the conversion:</p>
<div class="Bd Pp Bd-indent Li">
<pre>promgen -b -w -p bin -data_width 32 -u 0 design.bit -o design.bit.bin</pre>
</div>
</section>
<section class="Sh">
<h1 class="Sh" id="SYSCTL_VARIABLES"><a class="permalink" href="#SYSCTL_VARIABLES">SYSCTL
VARIABLES</a></h1>
<p class="Pp">The <code class="Nm">devcfg</code> driver provides the following
<a class="Xr">sysctl(8)</a> variables:</p>
<dl class="Bl-tag">
<dt id="hw.fpga.pl_done"><var class="Va">hw.fpga.pl_done</var></dt>
<dd>
<p class="Pp">This variable always reflects the status of the PL's DONE
signal. A 1 means the PL section has been properly programmed.</p>
</dd>
<dt id="hw.fpga.en_level_shifters"><var class="Va">hw.fpga.en_level_shifters</var></dt>
<dd>
<p class="Pp">This variable controls if the PS-PL level shifters are enabled
after the PL section has been reconfigured. This variable is 1 by
default but setting it to 0 allows the PL section to be programmed with
configurations that do not interface to the PS section of the part.
Changing this value has no effect on the level shifters until the next
device reconfiguration.</p>
</dd>
</dl>
</section>
<section class="Sh">
<h1 class="Sh" id="FILES"><a class="permalink" href="#FILES">FILES</a></h1>
<dl class="Bl-tag">
<dt><span class="Pa">/dev/devcfg</span></dt>
<dd>Character device for the <code class="Nm">devcfg</code> driver.</dd>
</dl>
</section>
<section class="Sh">
<h1 class="Sh" id="SEE_ALSO"><a class="permalink" href="#SEE_ALSO">SEE
ALSO</a></h1>
<p class="Pp">Zynq-7000 SoC Technical Reference Manual (Xilinx doc UG585)</p>
</section>
<section class="Sh">
<h1 class="Sh" id="AUTHORS"><a class="permalink" href="#AUTHORS">AUTHORS</a></h1>
<p class="Pp"><span class="An">Thomas Skibo</span></p>
</section>
</div>
<table class="foot">
<tr>
<td class="foot-date">February 28, 2013</td>
<td class="foot-os">FreeBSD 15.0</td>
</tr>
</table>
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