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+.\"	$OpenBSD: cpu.4,v 1.20 2024/09/10 17:01:09 tb Exp $
+.\"
+.\" Copyright (c) 2004 Ted Unangst
+.\" All rights reserved.
+.\"
+.\" Redistribution and use in source and binary forms, with or without
+.\" modification, are permitted provided that the following conditions
+.\" are met:
+.\" 1. Redistributions of source code must retain the above copyright
+.\"    notice, this list of conditions and the following disclaimer.
+.\" 2. Redistributions in binary form must reproduce the above copyright
+.\"    notice, this list of conditions and the following disclaimer in the
+.\"    documentation and/or other materials provided with the distribution.
+.\"
+.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+.\" IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+.\" OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+.\" IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+.\" INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+.\" NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+.\" DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+.\" THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+.\" (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+.\" THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+.\"
+.Dd $Mdocdate: September 10 2024 $
+.Dt CPU 4 i386
+.Os
+.Sh NAME
+.Nm cpu
+.Nd Central Processing Unit
+.Sh SYNOPSIS
+.Cd "cpu0 at mainbus?"
+.Cd "cpu* at mainbus?"
+.Sh DESCRIPTION
+Several processor models have additional features that extend their base
+functionality, such as power and frequency control or thermal monitoring.
+.Pp
+The
+.Xr sysctl 2
+.Va hw.cpuspeed
+returns the current operating frequency of the processor,
+though on some processors this value may be only an approximation.
+If possible, speed may be adjusted by altering
+.Va hw.setperf
+from 0 to 100,
+representing percentage of maximum speed.
+.Pp
+There are several possible implementations for speed adjustment,
+all transparent to the user.
+In systems with more than one control capability, they are preferred in the
+order given:
+.Bl -tag -width tenletters
+.It LongRun
+Found on Transmeta Crusoe processors, offering frequency scaling with numerous
+positions.
+The processor dynamically adjusts frequency in response to load; the setperf
+value is interpreted as the maximum.
+.It EST
+Enhanced SpeedStep found on Intel Pentium M processors,
+offering frequency scaling with numerous positions.
+.It SpeedStep
+Found on some Intel Pentium 3 and newer mobile chips,
+it is capable of adjusting frequency between a low and high value.
+It is only enabled on some chipsets.
+.It TCC
+Thermal Control Circuit found on Intel Pentium 4 and newer processors,
+it can adjust processor duty cycle in 12.5 percent increments.
+.It PowerNow
+Found on various AMD processors.
+It currently only supports a limited set of models
+in the K6, K7, and K8 families.
+.El
+.Pp
+The presence of extended instruction sets can be determined by the sysctl
+.Va machdep :
+.Bl -tag -width "tenletters"
+.It osfxsr
+Supports the fxsave instruction.
+.It sse
+Supports the SSE instruction set.
+.It sse2
+Supports the SSE2 instruction set.
+.It xcrypt
+Supports the VIA AES encryption instruction set.
+.El
+.Pp
+The sysctl
+.Va hw.sensors
+returns the current temperature reported by the processor.
+.Sh SEE ALSO
+.Xr sysctl 8
+.Sh BUGS
+Due to the way in which thermal information is reported on Intel processors,
+the temperature may be off by exactly +/-15 degrees C.
+.Pp
+For multiprocessor kernels with more than one CPU sensor,
+processors report identical temperatures
+since the temperature is taken from the processor running the sensors update.