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Diffstat (limited to 'static/openbsd/man4/man4.hppa/runway.4')
| -rw-r--r-- | static/openbsd/man4/man4.hppa/runway.4 | 65 |
1 files changed, 65 insertions, 0 deletions
diff --git a/static/openbsd/man4/man4.hppa/runway.4 b/static/openbsd/man4/man4.hppa/runway.4 new file mode 100644 index 00000000..b64ba6be --- /dev/null +++ b/static/openbsd/man4/man4.hppa/runway.4 @@ -0,0 +1,65 @@ +.\" $OpenBSD: runway.4,v 1.5 2007/05/31 19:19:54 jmc Exp $ +.\" +.\" Copyright (c) 2004 Michael Shalayeff +.\" All rights reserved. +.\" +.\" Redistribution and use in source and binary forms, with or without +.\" modification, are permitted provided that the following conditions +.\" are met: +.\" 1. Redistributions of source code must retain the above copyright +.\" notice, this list of conditions and the following disclaimer. +.\" 2. Redistributions in binary form must reproduce the above copyright +.\" notice, this list of conditions and the following disclaimer in the +.\" documentation and/or other materials provided with the distribution. +.\" +.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR +.\" IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +.\" OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +.\" IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, +.\" INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +.\" NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF MIND, +.\" USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +.\" THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +.\" (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +.\" THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +.\" +.Dd $Mdocdate: May 31 2007 $ +.Dt RUNWAY 4 hppa +.Os +.Sh NAME +.Nm runway +.Nd Runway bus +.Sh SYNOPSIS +.Cd "uturn* at mainbus?" +.Sh DESCRIPTION +The +.Nm +bus is a CPU and memory bus on systems based on the PA-7200, +PA-8000, and later CPUs. +The +.Nm +bus is a 64-bit multiplexed address/data bus with support for cache +coherency and allows up to 4-way SMP system configurations. +.Pp +One or two +.Xr uturn 4 +bridges connect the +.Nm +bus to the system's +.Xr gsc 4 +or +.Xr pci 4 +buses. +.Sh SEE ALSO +.Xr cpu 4 , +.Xr dino 4 , +.Xr gsc 4 , +.Xr intro 4 , +.Xr pci 4 , +.Xr uturn 4 +.Sh HISTORY +The +.Nm +driver +first appeared in +.Ox 3.7 . |
