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+.\"	$NetBSD: stpcide.4,v 1.8 2009/10/21 00:30:43 snj Exp $
+.\"
+.\" Copyright (c) 2003 Tohru Nishimura.
+.\"
+.\" Redistribution and use in source and binary forms, with or without
+.\" modification, are permitted provided that the following conditions
+.\" are met:
+.\" 1. Redistributions of source code must retain the above copyright
+.\"    notice, this list of conditions and the following disclaimer.
+.\" 2. Redistributions in binary form must reproduce the above copyright
+.\"    notice, this list of conditions and the following disclaimer in the
+.\"    documentation and/or other materials provided with the distribution.
+.\"
+.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+.\" IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+.\" OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+.\" IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+.\" INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+.\" NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+.\" DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+.\" THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+.\" INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+.\" THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+.\"
+.Dd October 31, 2003
+.Dt STPCIDE 4
+.Os
+.Sh NAME
+.Nm stpcide
+.Nd STMicroelectronics STPC IDE disk controllers driver
+.Sh SYNOPSIS
+.Cd "stpcide* at pci? dev ? function ? flags 0x0000"
+.Sh DESCRIPTION
+The
+.Nm
+driver supports the STMicroelectronics STPC x86 SoC internal IDE controllers,
+and provides the interface with the hardware for the
+.Xr ata 4
+driver.
+The driver features DMA mode 2 and PIO mode 4 transfer speeds.
+.Pp
+The 0x0002 flag forces the
+.Nm
+driver to disable DMA on chipsets for which DMA would normally be
+enabled.
+This can be used as a debugging aid, or to work around
+problems where the IDE controller is wired up to the system incorrectly.
+.Sh SEE ALSO
+.Xr ata 4 ,
+.Xr atapi 4 ,
+.Xr intro 4 ,
+.Xr pci 4 ,
+.Xr pciide 4 ,
+.Xr wd 4 ,
+.Xr wdc 4
+.Sh BUGS
+The timings used for the DMA and PIO modes are for STPC Atlas and
+its siblings with their PCI clock configured at 33 MHz.
+Other speeds including the STPC Vega Ultra-IDE controller will need
+adjustments.