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diff --git a/static/netbsd/man4/man4.x86/apic.4 4.html b/static/netbsd/man4/man4.x86/apic.4 4.html deleted file mode 100644 index 39537493..00000000 --- a/static/netbsd/man4/man4.x86/apic.4 4.html +++ /dev/null @@ -1,101 +0,0 @@ -<table class="head"> - <tr> - <td class="head-ltitle">APIC(4)</td> - <td class="head-vol">Device Drivers Manual (x86)</td> - <td class="head-rtitle">APIC(4)</td> - </tr> -</table> -<div class="manual-text"> -<section class="Sh"> -<h1 class="Sh" id="NAME"><a class="permalink" href="#NAME">NAME</a></h1> -<p class="Pp"><code class="Nm">apic</code>, <code class="Nm">ioapic</code>, - <code class="Nm">lapic</code> — <span class="Nd">Intel APIC - Architecture</span></p> -</section> -<section class="Sh"> -<h1 class="Sh" id="SYNOPSIS"><a class="permalink" href="#SYNOPSIS">SYNOPSIS</a></h1> -<p class="Pp"><code class="Cd">ioapic* at mainbus*</code></p> -</section> -<section class="Sh"> -<h1 class="Sh" id="DESCRIPTION"><a class="permalink" href="#DESCRIPTION">DESCRIPTION</a></h1> -<p class="Pp">The <code class="Nm">apic</code> subsystem provides basis for a - system of advanced programmable interrupt controllers (APICs) originally - designed by Intel but now widely used on all x86 systems.</p> -<p class="Pp">There are two elements in the architecture, the local APIC (LAPIC) - and the I/O APIC. Historically these were connected by a dedicated 3-wire - “APIC bus”, but the system bus is used for communication - today. The configuration is increasingly dependent on ACPI.</p> -<p class="Pp">Typically each CPU in the system contains one LAPIC that performs - two primary functions:</p> -<ol class="Bl-enum Bd-indent"> - <li>It receives interrupts both from internal sources and from the external - I/O APIC. The interrupt sources include I/O devices, the programmable APIC - timer, performance monitoring counters, thermal sensor interrupts, and - others.</li> - <li>In multiprocessor (MP) systems a LAPIC receives and sends interprocessor - interrupts (IPIs) from and to other processors in the system. IPIs are - used to provide software interrupts, interrupt forwarding, or preemptive - scheduling. Against this, the architecture can be generally seen as an - attempt to solve the interrupt routing efficiency issues in MP - systems.</li> -</ol> -<p class="Pp">There is typically one I/O APIC for each peripheral bus in the - system. Each I/O APIC has a series of interrupt inputs to external interrupt - sources. The architecture usually contains a redirection table which can be - used to route the interrupts that an I/O APIC receives to one or more local - APICs. When a LAPIC is able to accept an interrupt, it will signal the CPU. - Without an I/O APIC, the local APICs are therefore mostly useless; one of - the primary functions of the architecture is no longer achievable, - interrupts can not be distributed to different CPUs.</p> -<p class="Pp">The 8259 PIC has coexisted with the architecture since its - introduction. It is still possible to disable the APIC system and revert - back to a 8259-compatible PIC. But the widespread use of MP systems has made - this mainly a fallback option.</p> -</section> -<section class="Sh"> -<h1 class="Sh" id="SEE_ALSO"><a class="permalink" href="#SEE_ALSO">SEE - ALSO</a></h1> -<p class="Pp"><a class="Xr">acpi(4)</a>, <a class="Xr">mainbus(4)</a>, - <a class="Xr">x86/ichlpcib(4)</a></p> -<p class="Pp"><cite class="Rs"><span class="RsA">Intel Corporation</span>, - <span class="RsT">Intel 64 and IA-32 Architectures Software Developer's - Manual</span>, <span class="RsV">Volume 3A: System Programming Guide, Part - 1</span>, - <a class="RsU" href="http://www.intel.com/Assets/PDF/manual/253668.pdf">http://www.intel.com/Assets/PDF/manual/253668.pdf</a>, - <span class="RsP">Chapter 10</span>, <span class="RsD">January, - 2011</span>.</cite></p> -<p class="Pp"><cite class="Rs"><span class="RsA">Intel Corporation</span>, - <span class="RsT">Intel 82093AA I/O Advanced Programmable</span>, - <span class="RsT">Interrupt Controller (I/O APIC) Datasheet</span>, - <a class="RsU" href="http://www.intel.com/design/chipsets/datashts/29056601.pdf">http://www.intel.com/design/chipsets/datashts/29056601.pdf</a>, - <span class="RsD">May, 1996</span>.</cite></p> -<p class="Pp"><cite class="Rs"><span class="RsA">Intel Corporation</span>, - <span class="RsT">8259A, Programmable Interrupt Controller</span>, - <a class="RsU" href="http://pdos.csail.mit.edu/6.828/2005/readings/hardware/8259A.pdf">http://pdos.csail.mit.edu/6.828/2005/readings/hardware/8259A.pdf</a>, - <span class="RsD">December, 1988</span>.</cite></p> -<p class="Pp"><cite class="Rs"><span class="RsA">John Baldwin</span>, - <span class="RsT">PCI Interrupts for x86 Machines under FreeBSD</span>, - <a class="RsU" href="http://people.freebsd.org/~jhb/papers/bsdcan/2007/article.pdf">http://people.freebsd.org/~jhb/papers/bsdcan/2007/article.pdf</a>, - <span class="RsD">May 18-19, 2007</span>, <span class="RsO">Proceedings of - BSDCan 2007</span>.</cite></p> -<p class="Pp"><cite class="Rs"><span class="RsA">Microsoft Corporation</span>, - <span class="RsT">PCI IRQ Routing on a Multiprocessor ACPI System</span>, - <a class="RsU" href="http://www.microsoft.com/whdc/archive/acpi-mp.mspx">http://www.microsoft.com/whdc/archive/acpi-mp.mspx</a>, - <span class="RsD">December 4, 2001</span>.</cite></p> -</section> -<section class="Sh"> -<h1 class="Sh" id="AUTHORS"><a class="permalink" href="#AUTHORS">AUTHORS</a></h1> -<p class="Pp">Authors of the <span class="Ux">NetBSD</span> implementation of - the Intel APIC Architecture include <span class="An">Andrew Doran</span>, - <span class="An">Bill Sommerfeld</span>, <span class="An">Frank van der - Linden</span>, and <span class="An">Stefan Grefen</span>, among others. The - older 8259 PIC implementation is based on the work of - <span class="An">William Jolitz</span>.</p> -</section> -</div> -<table class="foot"> - <tr> - <td class="foot-date">February 17, 2017</td> - <td class="foot-os">NetBSD 10.1</td> - </tr> -</table> |