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diff --git a/static/freebsd/man7/simd.7 4.html b/static/freebsd/man7/simd.7 4.html new file mode 100644 index 00000000..7ef0f744 --- /dev/null +++ b/static/freebsd/man7/simd.7 4.html @@ -0,0 +1,458 @@ +<table class="head"> + <tr> + <td class="head-ltitle">SIMD(7)</td> + <td class="head-vol">Miscellaneous Information Manual</td> + <td class="head-rtitle">SIMD(7)</td> + </tr> +</table> +<div class="manual-text"> +<section class="Sh"> +<h1 class="Sh" id="NAME"><a class="permalink" href="#NAME">NAME</a></h1> +<p class="Pp"><code class="Nm">simd</code> — <span class="Nd">SIMD + enhancements</span></p> +</section> +<section class="Sh"> +<h1 class="Sh" id="DESCRIPTION"><a class="permalink" href="#DESCRIPTION">DESCRIPTION</a></h1> +<p class="Pp">On some architectures, the <span class="Ux">FreeBSD</span> + <i class="Em">libc</i> provides enhanced implementations of commonly used + functions, replacing the architecture-independent implementations used + otherwise. Depending on architecture and function, an enhanced + implementation of a function may either always be used or the + <i class="Em">libc</i> detects at runtime which SIMD instruction set + extensions are supported and picks the most suitable implementation + automatically. On <code class="Cm">amd64</code>, the environment variable + <code class="Ev">ARCHLEVEL</code> can be used to override this + mechanism.</p> +<p class="Pp">Enhanced functions are present for the following + architectures:</p> +<table class="Bl-column Bd-indent"> + <tr id="FUNCTION"> + <td><a class="permalink" href="#FUNCTION"><i class="Em">FUNCTION</i></a></td> + <td><a class="permalink" href="#AARCH64"><i class="Em" id="AARCH64">AARCH64</i></a></td> + <td><a class="permalink" href="#ARM"><i class="Em" id="ARM">ARM</i></a></td> + <td><a class="permalink" href="#AMD64"><i class="Em" id="AMD64">AMD64</i></a></td> + <td><a class="permalink" href="#I386"><i class="Em" id="I386">I386</i></a></td> + <td><a class="permalink" href="#PPC64"><i class="Em" id="PPC64">PPC64</i></a></td> + <td><a class="permalink" href="#RISC-V"><i class="Em" id="RISC-V">RISC-V</i></a></td> + </tr> + <tr> + <td>bcmp</td> + <td>A</td> + <td></td> + <td>S1</td> + <td>S</td> + </tr> + <tr> + <td>bcopy</td> + <td>A</td> + <td>S</td> + <td>S</td> + <td>S</td> + <td>SV</td> + <td>S</td> + </tr> + <tr> + <td>bzero</td> + <td>A</td> + <td>S</td> + <td>S</td> + <td>S</td> + <td></td> + <td>S</td> + </tr> + <tr> + <td>div</td> + <td></td> + <td></td> + <td>S</td> + <td>S</td> + </tr> + <tr> + <td>index</td> + <td>A</td> + <td></td> + <td>S1</td> + <td></td> + <td>S</td> + </tr> + <tr> + <td>ldiv</td> + <td></td> + <td></td> + <td>S</td> + <td>S</td> + </tr> + <tr> + <td>lldiv</td> + <td></td> + <td></td> + <td>S</td> + </tr> + <tr> + <td>memchr</td> + <td>A</td> + <td></td> + <td>S1</td> + <td></td> + <td></td> + <td>S</td> + </tr> + <tr> + <td>memcmp</td> + <td>A</td> + <td>S</td> + <td>S1</td> + <td>S</td> + </tr> + <tr> + <td>memccpy</td> + <td>A</td> + <td></td> + <td>S1</td> + </tr> + <tr> + <td>memcpy</td> + <td>AM</td> + <td>S</td> + <td>S</td> + <td>S</td> + <td>SV</td> + <td>S</td> + </tr> + <tr> + <td>memmove</td> + <td>AM</td> + <td>S</td> + <td>S</td> + <td>S</td> + <td>SV</td> + </tr> + <tr> + <td>memrchr</td> + <td>A</td> + <td></td> + <td>S1</td> + </tr> + <tr> + <td>memset</td> + <td>AM</td> + <td>S</td> + <td>S</td> + <td>S</td> + <td></td> + <td>S</td> + </tr> + <tr> + <td>rindex</td> + <td>A</td> + <td></td> + <td>S1</td> + <td>S</td> + <td></td> + <td>S</td> + </tr> + <tr> + <td>stpcpy</td> + <td>A</td> + <td></td> + <td>S1</td> + </tr> + <tr> + <td>stpncpy</td> + <td></td> + <td></td> + <td>S1</td> + </tr> + <tr> + <td>strcat</td> + <td>A</td> + <td></td> + <td>S1</td> + <td>S</td> + </tr> + <tr> + <td>strchr</td> + <td>A</td> + <td></td> + <td>S1</td> + <td>S</td> + <td></td> + <td>S</td> + </tr> + <tr> + <td>strchrnul</td> + <td>A</td> + <td></td> + <td>S1</td> + <td></td> + <td></td> + <td>S</td> + </tr> + <tr> + <td>strcmp</td> + <td>A</td> + <td>S</td> + <td>S1</td> + <td>S</td> + </tr> + <tr> + <td>strcpy</td> + <td>A</td> + <td></td> + <td>S1</td> + <td>S</td> + <td>S2</td> + </tr> + <tr> + <td>strcspn</td> + <td>S</td> + <td></td> + <td>S2</td> + </tr> + <tr> + <td>strlcat</td> + <td>A</td> + <td></td> + <td>S1</td> + </tr> + <tr> + <td>strlcpy</td> + <td>A</td> + <td></td> + <td>S1</td> + </tr> + <tr> + <td>strlen</td> + <td>A</td> + <td>S</td> + <td>S1</td> + <td></td> + <td></td> + <td>S</td> + </tr> + <tr> + <td>strncat</td> + <td>A</td> + <td></td> + <td>S1</td> + </tr> + <tr> + <td>strncmp</td> + <td>A</td> + <td>S</td> + <td>S1</td> + <td>S</td> + </tr> + <tr> + <td>strncpy</td> + <td></td> + <td></td> + <td>S1</td> + <td></td> + <td>S2</td> + </tr> + <tr> + <td>strnlen</td> + <td>A</td> + <td></td> + <td>S1</td> + <td></td> + <td></td> + <td>S</td> + </tr> + <tr> + <td>strrchr</td> + <td>A</td> + <td></td> + <td>S1</td> + <td>S</td> + <td></td> + <td>S</td> + </tr> + <tr> + <td>strpbrk</td> + <td>S</td> + <td></td> + <td>S2</td> + </tr> + <tr> + <td>strsep</td> + <td>S</td> + <td></td> + <td>S2</td> + </tr> + <tr> + <td>strspn</td> + <td>S</td> + <td></td> + <td>S2</td> + </tr> + <tr> + <td>swab</td> + <td></td> + <td></td> + <td></td> + <td>S</td> + </tr> + <tr> + <td>timingsafe_bcmp</td> + <td>A</td> + <td></td> + <td>S1</td> + </tr> + <tr> + <td>timingsafe_memcmp</td> + <td>S</td> + <td></td> + <td>S</td> + </tr> + <tr> + <td>wcschr</td> + <td></td> + <td></td> + <td></td> + <td>S</td> + </tr> + <tr> + <td>wcscmp</td> + <td></td> + <td></td> + <td></td> + <td>S</td> + </tr> + <tr> + <td>wcslen</td> + <td></td> + <td></td> + <td></td> + <td>S</td> + </tr> + <tr> + <td>wmemchr</td> + <td></td> + <td></td> + <td></td> + <td>S</td> + </tr> +</table> +<p class="Pp" id="S"><a class="permalink" href="#S"><b class="Sy">S</b></a>: scalar + (non-SIMD), + <a class="permalink" href="#1"><b class="Sy" id="1">1</b></a>: amd64 + baseline, + <a class="permalink" href="#2"><b class="Sy" id="2">2</b></a>: x86-64-v2 + or PowerPC 2.05, + <a class="permalink" href="#3"><b class="Sy" id="3">3</b></a>: x86-64-v3, + <a class="permalink" href="#4"><b class="Sy" id="4">4</b></a>: x86-64-v4, + <a class="permalink" href="#V"><b class="Sy" id="V">V</b></a>: PowerPC VSX, + <a class="permalink" href="#A"><b class="Sy" id="A">A</b></a>: Arm ASIMD + (NEON), + <a class="permalink" href="#M"><b class="Sy" id="M">M</b></a>: Arm MOPS.</p> +</section> +<section class="Sh"> +<h1 class="Sh" id="ENVIRONMENT"><a class="permalink" href="#ENVIRONMENT">ENVIRONMENT</a></h1> +<dl class="Bl-tag"> + <dt id="ARCHLEVEL"><a class="permalink" href="#ARCHLEVEL"><code class="Ev">ARCHLEVEL</code></a></dt> + <dd>On + <a class="permalink" href="#amd64"><i class="Em" id="amd64">amd64</i></a>, + controls the level of SIMD enhancements used. If this variable is set to + an architecture level from the list below and that architecture level is + supported by the processor, SIMD enhancements up to + <code class="Ev">ARCHLEVEL</code> are used. If + <code class="Ev">ARCHLEVEL</code> is unset, not recognised, or not + supported by the processor, the highest level of SIMD enhancements + supported by the processor is used. + <p class="Pp">A suffix beginning with ‘:’ or ‘+’ + in <code class="Ev">ARCHLEVEL</code> is ignored and may be used for + future extensions. The architecture level can be prefixed with a + ‘!’ character to force use of the requested architecture + level, even if the processor does not advertise that it is supported. + This usually causes applications to crash and should only be used for + testing purposes or if architecture level detection yields incorrect + results.</p> + <p class="Pp">The architecture levels follow the AMD64 SysV ABI + supplement:</p> + <dl class="Bl-tag"> + <dt id="scalar"><a class="permalink" href="#scalar"><code class="Cm">scalar</code></a></dt> + <dd>scalar enhancements only (no SIMD)</dd> + <dt id="baseline"><a class="permalink" href="#baseline"><code class="Cm">baseline</code></a></dt> + <dd>cmov, cx8, x87 FPU, fxsr, MMX, osfxsr, SSE, SSE2</dd> + <dt id="x86-64-v2"><a class="permalink" href="#x86-64-v2"><code class="Cm">x86-64-v2</code></a></dt> + <dd>cx16, lahf/sahf, popcnt, SSE3, SSSE3, SSE4.1, SSE4.2</dd> + <dt id="x86-64-v3"><a class="permalink" href="#x86-64-v3"><code class="Cm">x86-64-v3</code></a></dt> + <dd>AVX, AVX2, BMI1, BMI2, F16C, FMA, lzcnt, movbe, osxsave</dd> + <dt id="x86-64-v4"><a class="permalink" href="#x86-64-v4"><code class="Cm">x86-64-v4</code></a></dt> + <dd>AVX-512F/BW/CD/DQ/VL</dd> + </dl> + </dd> +</dl> +</section> +<section class="Sh"> +<h1 class="Sh" id="DIAGNOSTICS"><a class="permalink" href="#DIAGNOSTICS">DIAGNOSTICS</a></h1> +<dl class="Bl-diag"> + <dt>Illegal Instruction</dt> + <dd>Printed by <a class="Xr">sh(1)</a> if a command is terminated through + delivery of a <code class="Dv">SIGILL</code> signal, see + <a class="Xr">signal(3)</a>. + <p class="Pp">Use of an unsupported architecture level was forced by setting + <code class="Ev">ARCHLEVEL</code> to a string beginning with a + ‘!’ character, causing a process to crash due to use of an + unsupported instruction. Unset <code class="Ev">ARCHLEVEL</code>, remove + the ‘!’ prefix or select a supported architecture + level.</p> + <p class="Pp">Message may also appear for unrelated reasons.</p> + </dd> +</dl> +</section> +<section class="Sh"> +<h1 class="Sh" id="SEE_ALSO"><a class="permalink" href="#SEE_ALSO">SEE + ALSO</a></h1> +<p class="Pp"><a class="Xr">string(3)</a>, <a class="Xr">arch(7)</a></p> +<p class="Pp"><cite class="Rs"><span class="RsA">H. J. Lu</span>, + <span class="RsA">Michael Matz</span>, <span class="RsA">Milind + Girkar</span>, <span class="RsA">Jan Hubička</span>, + <span class="RsA">Andreas Jaeger</span>, and <span class="RsA">Mark + Mitchell</span>, <span class="RsT">AMD64 Architecture Processor + Supplement</span>, <i class="RsB">System V Application Binary Interface</i>, + <span class="RsD">May 23, 2023</span>, <span class="RsO">Version + 1.0</span>.</cite></p> +</section> +<section class="Sh"> +<h1 class="Sh" id="HISTORY"><a class="permalink" href="#HISTORY">HISTORY</a></h1> +<p class="Pp">Architecture-specific enhanced <i class="Em">libc</i> functions + were added starting with <span class="Ux">FreeBSD 2.0</span> for + <code class="Cm">i386</code>, <span class="Ux">FreeBSD 6.0</span> for + <code class="Cm">arm</code>, <span class="Ux">FreeBSD 6.1</span> for + <code class="Cm">amd64</code>, <span class="Ux">FreeBSD 11.0</span> for + <code class="Cm">aarch64</code>, <span class="Ux">FreeBSD 12.0</span> for + <code class="Cm">powerpc64</code>, and <span class="Ux">FreeBSD 16.0</span> + for <code class="Cm">riscv64</code>. SIMD-enhanced functions were first + added with <span class="Ux">FreeBSD 13.0</span> for + <code class="Cm">powerpc64</code> and with <span class="Ux">FreeBSD + 14.1</span> for <code class="Cm">amd64</code>.</p> +<p class="Pp">A <code class="Nm">simd</code> manual page appeared in + <span class="Ux">FreeBSD 14.1</span>.</p> +</section> +<section class="Sh"> +<h1 class="Sh" id="AUTHOR"><a class="permalink" href="#AUTHOR">AUTHOR</a></h1> +<p class="Pp"><span class="An">Robert Clausecker</span> + <<a class="Mt" href="mailto:fuz@FreeBSD.org">fuz@FreeBSD.org</a>></p> +</section> +<section class="Sh"> +<h1 class="Sh" id="CAVEATS"><a class="permalink" href="#CAVEATS">CAVEATS</a></h1> +<p class="Pp">Other parts of <span class="Ux">FreeBSD</span> such as + cryptographic routines in the kernel or in OpenSSL may also use SIMD + enhancements. These enhancements are not subject to the + <code class="Ev">ARCHLEVEL</code> variable and may have their own + configuration mechanism.</p> +</section> +<section class="Sh"> +<h1 class="Sh" id="BUGS"><a class="permalink" href="#BUGS">BUGS</a></h1> +<p class="Pp">Use of SIMD enhancements cannot be configured on powerpc64.</p> +</section> +</div> +<table class="foot"> + <tr> + <td class="foot-date">October 21, 2025</td> + <td class="foot-os">FreeBSD 15.0</td> + </tr> +</table> |