12 files changed, 1050 insertions, 0 deletions

diff --git a/static/freebsd/man4/man4.arm/Makefile b/static/freebsd/man4/man4.arm/Makefile
new file mode 100644
index 00000000..4bdc15c4
--- /dev/null
+++ b/static/freebsd/man4/man4.arm/Makefile
@@ -0,0 +1,3 @@
+MAN = $(wildcard *.4)
+
+include ../../../mandoc.mk
diff --git a/static/freebsd/man4/man4.arm/am335x_dmtpps.4 b/static/freebsd/man4/man4.arm/am335x_dmtpps.4
new file mode 100644
index 00000000..bec5ff77
--- /dev/null
+++ b/static/freebsd/man4/man4.arm/am335x_dmtpps.4
@@ -0,0 +1,161 @@
+.\"
+.\" Copyright (c) 2015 Ian Lepore <ian@freebsd.org>
+.\" All rights reserved.
+.\"
+.\" Redistribution and use in source and binary forms, with or without
+.\" modification, are permitted provided that the following conditions
+.\" are met:
+.\"
+.\" 1. Redistributions of source code must retain the above copyright
+.\"    notice, this list of conditions and the following disclaimer.
+.\" 2. Redistributions in binary form must reproduce the above copyright
+.\"    notice, this list of conditions and the following disclaimer in the
+.\"    documentation and/or other materials provided with the distribution.
+.\"
+.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+.\" IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+.\" OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+.\" IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+.\" INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+.\" NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+.\" DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+.\" THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+.\" (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+.\" THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+.\"
+.Dd August 12, 2015
+.Dt AM335X_DMTPPS 4 arm
+.Os
+.Sh NAME
+.Nm am335x_dmtpps
+.Nd RFC 2783 Pulse Per Second API driver for AM335x systems
+.Sh SYNOPSIS
+.Cd "device am335x_dmtpps"
+.Pp
+Optional in
+.Pa /boot/loader.conf :
+.Cd hw.am335x_dmtpps.input="pin name"
+.\"
+.Sh DESCRIPTION
+The
+.Nm
+device driver provides a system time counter that includes precise
+capture of Pulse Per Second (PPS) signals emitted by GPS receivers
+and other timing devices.
+The
+.Nm
+driver may be compiled into the kernel or loaded as a module.
+.Pp
+The AM335x timer hardware captures the value of the system time counter
+on the leading edge of the PPS pulse.
+Because the capture is done by the hardware there is no interrupt
+latency in the measurement.
+The time counter runs at 24Mhz, providing a measurement resolution
+of 42 nanoseconds.
+.Pp
+To use the PPS timing information provided by this driver with
+.Xr ntpd 8 ,
+symlink the
+.Pa /dev/dmtpps
+device to
+.Pa /dev/pps0
+and configure server
+.Va 127.127.22.0
+in
+.Xr ntp.conf 5
+to configure a type 22 (ATOM) refclock.
+.\"
+.Sh DRIVER CONFIGURATION
+The AM335x hardware provides four timer devices with a capture input
+pin, DMTimer4 through DMTimer7.
+Because it also provides the active system time counter,
+only one instance of the
+.Nm
+driver can be active at a time.
+The driver uses system pin configuration to determine which hardware
+timer device to use.
+Configure the timer input pin in the system's FDT data, or by
+supplying the pin name using a tunable variable in
+.Xr loader.conf 5 .
+.Pp
+To use a standard kernel and FDT data, use
+.Xr loader.conf 5
+to load the
+.Nm
+module and set the
+.Va hw.am335x_dmtpps.input
+tunable variable to the name of the input pin, one of the following:
+.Pp
+.Bl -tag -width "GPMC_ADVn_ALE MMMM" -offset MMMM -compact
+.It Em Name
+.Em Hardware
+.It P8-7
+DMTimer4; Beaglebone P8 header pin 7.
+.It P8-8
+DMTimer7; Beaglebone P8 header pin 8.
+.It P8-9
+DMTimer5; Beaglebone P8 header pin 9.
+.It P8-10
+DMTimer6; Beaglebone P8 header pin 10.
+.It GPMC_ADVn_ALE
+DMTimer4.
+.It GPMC_BEn0_CLE
+DMTimer5.
+.It GPMC_WEn
+DMTimer6.
+.It GPMC_OEn_REn
+DMTimer7.
+.El
+.Pp
+To configure the
+.Nm
+driver using FDT data, create a new pinctrl node by referencing the standard
+.Va am33xx_pinmux
+driver node (which is defined in am33xx.dtsi) in your dts file.
+For example:
+.Bd -literal
+   &am33xx_pinmux {
+      timer4_pins: timer4_pins {
+         pinctrl-single,pins = <0x90 (PIN_INPUT | MUX_MODE2)>;
+      };
+   };
+.Ed
+.Pp
+Add pinctrl properties referencing
+.Va timer4_pins
+to the standard
+.Va timer4
+device node (also defined in am33xx.dtsi) by referencing it in
+your dts file as follows:
+.Bd -literal
+   &timer4 {
+      pinctrl-names = "default";
+      pinctrl-0 = <&timer4_pins>;
+   };
+.Ed
+.\"
+.Sh FILES
+.Bl -tag -width ".Pa /dev/dmtpps" -compact
+.It Pa /dev/dmtpps
+The device providing
+.Xr ioctl 2
+access to the RFC 2783 API.
+.El
+.\"
+.Sh SEE ALSO
+.Xr timecounters 4 ,
+.Xr loader.conf 5 ,
+.Xr ntp.conf 5 ,
+.Xr ntpd 8
+.\"
+.Sh HISTORY
+The
+.Nm
+device driver first appeared in
+.Fx 11.0 .
+.\"
+.Sh AUTHORS
+The
+.Nm
+device driver and this manual page were written by
+.An Ian Lepore Aq Mt ian@FreeBSD.org .
diff --git a/static/freebsd/man4/man4.arm/ar40xx.4 b/static/freebsd/man4/man4.arm/ar40xx.4
new file mode 100644
index 00000000..e314d30d
--- /dev/null
+++ b/static/freebsd/man4/man4.arm/ar40xx.4
@@ -0,0 +1,35 @@
+.\"
+.\" Copyright (c) 2025 Alexander Ziaee
+.\"
+.\" SPDX-License-Identifier: BSD-2-Clause
+.\"
+.Dd May 10, 2025
+.Dt AR40XX 4 arm
+.Sh NAME
+.Nm ar40xx_switch
+.Nd Qualcomm IPQ4018/IPQ4019 Gigabit Ethernet switch driver
+.Sh SYNOPSIS
+.Cd device mdio
+.Cd etherswitch
+.Cd ar40xx_switch
+.Sh DESCRIPTION
+The
+.Nm
+driver supports the Gigabit Ethernet switch inside the
+Qualcomm IPQ4018/IPQ4019 SoC.
+.Sh HARDWARE
+The
+.Nm
+driver supports the following Gigabit Ethernet switch controllers:
+.Pp
+.Bl -bullet -compact
+.It
+Qualcomm IPQ 4019 Five-port Gigabit Ethernet Switch
+.It
+Qualcomm IPQ 4018 Five-port Gigabit Ethernet Switch
+.El
+.Sh SEE ALSO
+.Xr etherswitch 4 ,
+.Xr etherswitchcfg 8
+.Sh CAVEATS
+This driver currently only supports L2 port/VLAN mapping modes.
diff --git a/static/freebsd/man4/man4.arm/bcm283x_pwm.4 b/static/freebsd/man4/man4.arm/bcm283x_pwm.4
new file mode 100644
index 00000000..71d7f0cc
--- /dev/null
+++ b/static/freebsd/man4/man4.arm/bcm283x_pwm.4
@@ -0,0 +1,108 @@
+.\"
+.\" SPDX-License-Identifier: BSD-2-Clause
+.\"
+.\" Copyright (c) 2017 Poul-Henning Kamp <phk@FreeBSD.org>
+.\" All rights reserved.
+.\"
+.\" Redistribution and use in source and binary forms, with or without
+.\" modification, are permitted provided that the following conditions
+.\" are met:
+.\" 1. Redistributions of source code must retain the above copyright
+.\"    notice, this list of conditions and the following disclaimer.
+.\" 2. Redistributions in binary form must reproduce the above copyright
+.\"    notice, this list of conditions and the following disclaimer in the
+.\"    documentation and/or other materials provided with the distribution.
+.\"
+.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+.\" IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+.\" OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+.\" IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+.\" INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+.\" NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+.\" DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+.\" THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+.\" (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+.\" THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+.\"
+.Dd September 10, 2018
+.Dt BCM283X_PWM 4 arm
+.Os
+.Sh NAME
+.Nm bcm283x_pwm
+.Nd bcm283x_pwm - driver for Raspberry Pi 2/3 PWM
+.Sh SYNOPSIS
+.Cd "kldload bcm283x_clkman"
+.Cd "kldload bcm283x_pwm"
+.Sh DESCRIPTION
+The
+.Nm
+driver provides access to the PWM engine on GPIO12 of Raspberry Pi 2 and 3 hardware.
+.Pp
+The PWM hardware is controlled via the
+.Xr sysctl 8
+interface:
+.Bd -literal
+dev.pwm.0.mode: 1
+dev.pwm.0.mode2: 1
+dev.pwm.0.freq: 125000000
+dev.pwm.0.ratio: 2500
+dev.pwm.0.ratio2: 2500
+dev.pwm.0.period: 10000
+dev.pwm.0.period2: 10000
+dev.pwm.0.pwm_freq: 12500
+dev.pwm.0.pwm_freq2: 12500
+.Ed
+.Bl -tag -width ".Va dev.pwm"
+.It Va dev.pwm.0.mode , dev.pwm.0.mode2
+PWM Mode for channels 1 and 2.
+Three modes exist, 0=off, 1=PWM, 2=N/M.
+The N/M mode is a first order delta-sigma mode, which makes a quite
+handy DAC output with a trivial RC lowpass filter.
+.Pp
+.It Va dev.pwm.0.freq
+The input frequency to the PWM hardware in Hz.
+Applies to both channels 1 and 2.
+Minimum frequency is 123 kHz, maximum frequency is 125 MHz.
+.It Va dev.pwm.0.period , dev.pwm.0.period2
+The period length in cycles.
+In PWM mode, the output frequencies will be
+(
+.Va dev.pwm.0.freq
+/
+.Va dev.pwm.period
+) and (
+.Va dev.pwm.0.freq2
+/
+.Va dev.pwm.0.period2
+).
+In N/M mode this is the 'M'.
+.It Va dev.pwm.0.ratio , dev.pwm.0.ratio2
+The "on" period in cycles for PWM channels 1 and 2.
+In PWM mode, to get a 25% dutycycle, set this to 25% of
+.Va dev.pwm.0.period
+or
+.Va dev.pwm.0.period2 ,
+as appropriate.
+In N/M mode this is the 'N'.
+.It Va dev.pwm.0.pwm_freq , dev.pwm.0.pwm_freq2
+The calculated PWM output frequencies in PWM mode, for channels 1 and 2.
+.El
+.Pp
+.Sh NOTES
+Currently the
+.Nm
+driver ignores the 'status="disabled"' flag in the DTB, assuming that
+if you load the driver, you want it to work.
+.Sh SEE ALSO
+.Xr sysctl 8
+.Sh HISTORY
+The
+.Nm
+driver first appeared in
+.Fx 12.0 .
+.Sh AUTHORS
+.An -nosplit
+The
+.Nm
+driver and this manual page were written by
+.An Poul-Henning Kamp Aq Mt phk@FreeBSD.org .
diff --git a/static/freebsd/man4/man4.arm/devcfg.4 b/static/freebsd/man4/man4.arm/devcfg.4
new file mode 100644
index 00000000..cbc20581
--- /dev/null
+++ b/static/freebsd/man4/man4.arm/devcfg.4
@@ -0,0 +1,93 @@
+.\"
+.\" Copyright (c) 2013 Thomas Skibo
+.\" All rights reserved.
+.\"
+.\" Redistribution and use in source and binary forms, with or without
+.\" modification, are permitted provided that the following conditions
+.\" are met:
+.\" 1. Redistributions of source code must retain the above copyright
+.\"    notice, this list of conditions and the following disclaimer.
+.\" 2. The name of the author may not be used to endorse or promote products
+.\"    derived from this software without specific prior written permission.
+.\"
+.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+.\" ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+.\" SUCH DAMAGE.
+.\"
+.Dd February 28, 2013
+.Dt DEVCFG 4 arm
+.Os
+.Sh NAME
+.Nm devcfg
+.Nd Zynq PL device config interface
+.Sh SYNOPSIS
+.Cd device devcfg
+.Sh DESCRIPTION
+The special file
+.Pa /dev/devcfg
+can be used to configure the PL (FPGA) section of the Xilinx Zynq-7000.
+.Pp
+On the first write to the character device at file offset 0, the
+.Nm
+driver
+asserts the top-level PL reset signals, disables the PS-PL level shifters,
+and clears the PL configuration.
+Write data is sent to the PCAP (processor configuration access port).
+When the PL asserts the DONE signal, the devcfg driver will enable the level
+shifters and release the top-level PL reset signals.
+.Pp
+The PL (FPGA) can be configured by writing the bitstream to the character
+device like this:
+.Bd -literal -offset indent
+cat design.bit.bin > /dev/devcfg
+.Ed
+.Pp
+The file should not be confused with the .bit file output by the FPGA
+design tools.
+It is the binary form of the configuration bitstream.
+The Xilinx
+.Ic promgen
+tool can do the conversion:
+.Bd -literal -offset indent
+promgen -b -w -p bin -data_width 32 -u 0 design.bit -o design.bit.bin
+.Ed
+.Sh SYSCTL VARIABLES
+The
+.Nm
+driver provides the following
+.Xr sysctl 8
+variables:
+.Bl -tag -width 4n
+.It Va hw.fpga.pl_done
+.Pp
+This variable always reflects the status of the PL's DONE signal.
+A 1 means the PL section has been properly programmed.
+.It Va hw.fpga.en_level_shifters
+.Pp
+This variable controls if the PS-PL level shifters are enabled after the
+PL section has been reconfigured.
+This variable is 1 by default but setting it to 0 allows the PL section to be
+programmed with configurations that do not interface to the PS section of the
+part.
+Changing this value has no effect on the level shifters until the next device
+reconfiguration.
+.El
+.Sh FILES
+.Bl -tag -width 12n
+.It Pa /dev/devcfg
+Character device for the
+.Nm
+driver.
+.El
+.Sh SEE ALSO
+Zynq-7000 SoC Technical Reference Manual (Xilinx doc UG585)
+.Sh AUTHORS
+.An Thomas Skibo
diff --git a/static/freebsd/man4/man4.arm/dwcotg.4 b/static/freebsd/man4/man4.arm/dwcotg.4
new file mode 100644
index 00000000..e6e8c797
--- /dev/null
+++ b/static/freebsd/man4/man4.arm/dwcotg.4
@@ -0,0 +1,29 @@
+.\"
+.\" Copyright (c) 2025 Alexander Ziaee
+.\"
+.\" SPDX-License-Identifier: BSD-2-Clause
+.\"
+.Dd November 5, 2025
+.Dt DWCOTG 4 arm
+.Os
+.Sh NAME
+.Nm dwcotg
+.Nd Synopsys DesignWare USB controller driver
+.Sh SYNOPSIS
+.Cd device acpi
+.Cd device fdt
+.Cd device dwcotg
+.Sh HARDWARE
+The
+.Nm
+driver supports the
+Synopsys DesignWare USB controller found in many embedded devices.
+.Sh SEE ALSO
+.Xr usb_template 4
+.Sh HISTORY
+The
+.Nm
+driver appeared in
+.Fx 10.0 .
+.Sh AUTHORS
+.An Hans Petter Selasky
diff --git a/static/freebsd/man4/man4.arm/imx6_ahci.4 b/static/freebsd/man4/man4.arm/imx6_ahci.4
new file mode 100644
index 00000000..50689e32
--- /dev/null
+++ b/static/freebsd/man4/man4.arm/imx6_ahci.4
@@ -0,0 +1,63 @@
+.\"
+.\" Copyright (c) 2018 Ian Lepore <ian@freebsd.org>
+.\" All rights reserved.
+.\"
+.\" Redistribution and use in source and binary forms, with or without
+.\" modification, are permitted provided that the following conditions
+.\" are met:
+.\"
+.\" 1. Redistributions of source code must retain the above copyright
+.\"    notice, this list of conditions and the following disclaimer.
+.\" 2. Redistributions in binary form must reproduce the above copyright
+.\"    notice, this list of conditions and the following disclaimer in the
+.\"    documentation and/or other materials provided with the distribution.
+.\"
+.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+.\" IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+.\" OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+.\" IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+.\" INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+.\" NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+.\" DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+.\" THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+.\" (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+.\" THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+.\"
+.Dd July 7, 2018
+.Dt IMX6_AHCI 4 arm
+.Os
+.Sh NAME
+.Nm imx6_ahci
+.Nd device driver for the NXP i.MX6 on-chip SATA controller
+.Sh SYNOPSIS
+To compile this driver into the kernel,
+place the following line in your
+kernel configuration file:
+.Bd -ragged -offset indent
+.Cd "device ahci"
+.Ed
+.Pp
+Alternatively, to load the driver as a
+module at boot time, place the following line in
+.Xr loader.conf 5 :
+.Bd -literal -offset indent
+imx6_ahci_load="YES"
+.Ed
+.Sh DESCRIPTION
+The
+.Nm
+driver provides
+support for the on-chip SATA controller found on some models of
+the NXP i.MX6 chip.
+The driver is a thin glue layer to interpret the platform's FDT
+data and marshall resources for the standard
+.Xr ahci 4
+driver.
+.Sh SEE ALSO
+.Xr ahci 4 ,
+.Xr fdt 4
+.Sh HISTORY
+The
+.Nm
+driver first appeared in
+.Fx 12.0 .
diff --git a/static/freebsd/man4/man4.arm/imx6_snvs.4 b/static/freebsd/man4/man4.arm/imx6_snvs.4
new file mode 100644
index 00000000..2c1db97b
--- /dev/null
+++ b/static/freebsd/man4/man4.arm/imx6_snvs.4
@@ -0,0 +1,76 @@
+.\"
+.\" Copyright (c) 2018 Ian Lepore <ian@freebsd.org>
+.\" All rights reserved.
+.\"
+.\" Redistribution and use in source and binary forms, with or without
+.\" modification, are permitted provided that the following conditions
+.\" are met:
+.\"
+.\" 1. Redistributions of source code must retain the above copyright
+.\"    notice, this list of conditions and the following disclaimer.
+.\" 2. Redistributions in binary form must reproduce the above copyright
+.\"    notice, this list of conditions and the following disclaimer in the
+.\"    documentation and/or other materials provided with the distribution.
+.\"
+.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+.\" IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+.\" OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+.\" IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+.\" INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+.\" NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+.\" DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+.\" THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+.\" (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+.\" THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+.\"
+.Dd July 8, 2018
+.Dt IMX6_SNVS 4 arm
+.Os
+.Sh NAME
+.Nm imx6_snvs
+.Nd device driver for the NXP i.MX6 on-chip Realtime Clock
+.Sh SYNOPSIS
+To compile this driver into the kernel,
+place the following line in your
+kernel configuration file:
+.Bd -ragged -offset indent
+.Cd "device imx6_snvs"
+.Ed
+.Pp
+Alternatively, to load the driver as a
+module at boot time, place the following line in
+.Xr loader.conf 5 :
+.Bd -literal -offset indent
+imx6_snvs_load="YES"
+.Ed
+.Sh DESCRIPTION
+The
+.Nm
+driver provides
+support for the i.MX6 on-chip realtime clock.
+It provides the time of day with a resolution of approximately
+30 microseconds.
+.Pp
+.Sq SNVS
+stands for Secure Non-Volatile Storage, and refers to the subsystem
+within the chip that (optionally) remains powered by a battery when
+the rest of the system is powered down.
+The on-chip realtime clock is part of that subsystem.
+Other features of the SNVS subsystem are related to security, tamper
+monitoring, and power control; the
+.Nm
+driver does not currently support those features.
+.Pp
+Many i.MX6 systems do not use a battery to provide power to the SNVS
+due to its relatively high power draw.  In such systems, this driver
+is able to provide a very accurate time following a reboot, but cannot
+provide time at all if the power is cycled.  If the system provides an
+i2c or other type of alternate realtime clock with lower resolution,
+there is value in configuring both clock drivers.
+Doing so allows SNVS to provide accurate time after a reboot, while the
+external clock provides approximate time after power cycling.
+.Sh HISTORY
+The
+.Nm
+driver first appeared in
+.Fx 12.0 .
diff --git a/static/freebsd/man4/man4.arm/imx_spi.4 b/static/freebsd/man4/man4.arm/imx_spi.4
new file mode 100644
index 00000000..54a5339e
--- /dev/null
+++ b/static/freebsd/man4/man4.arm/imx_spi.4
@@ -0,0 +1,88 @@
+.\"
+.\" Copyright (c) 2018 Ian Lepore <ian@freebsd.org>
+.\" All rights reserved.
+.\"
+.\" Redistribution and use in source and binary forms, with or without
+.\" modification, are permitted provided that the following conditions
+.\" are met:
+.\"
+.\" 1. Redistributions of source code must retain the above copyright
+.\"    notice, this list of conditions and the following disclaimer.
+.\" 2. Redistributions in binary form must reproduce the above copyright
+.\"    notice, this list of conditions and the following disclaimer in the
+.\"    documentation and/or other materials provided with the distribution.
+.\"
+.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+.\" IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+.\" OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+.\" IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+.\" INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+.\" NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+.\" DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+.\" THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+.\" (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+.\" THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+.\"
+.Dd July 9, 2018
+.Dt IMX_SPI 4 arm
+.Os
+.Sh NAME
+.Nm imx_spi
+.Nd device driver for the NXP i.MX family Serial Peripheral Interface (SPI)
+.Sh SYNOPSIS
+To compile this driver into the kernel,
+place the following line in your
+kernel configuration file:
+.Bd -ragged -offset indent
+.Cd "device imx_spi"
+.Ed
+.Pp
+Alternatively, to load the driver as a
+module at boot time, place the following line in
+.Xr loader.conf 5 :
+.Bd -literal -offset indent
+imx_spi_load="YES"
+.Ed
+.Sh DESCRIPTION
+The
+.Nm
+driver provides support for the
+.Sq ECSPI
+(Enhanced Configurable SPI) hardware present on the NXP i.MX family
+of processors.
+While the ECSPI hardware supports both master and slave mode,
+this driver currently operates only in master mode.
+.Pp
+Due to hardware quirks, the
+.Nm
+driver requires that all chip select pins be configured as GPIO pins.
+Use the FDT property
+.Sq cs-gpios
+to specify which pins to use as chip selects.
+You may use any GPIO pins, including the ones that the hardware would
+normally use as SPI select pins; just configure them as GPIO in the
+.Xr fdt_pinctrl 4
+data.
+.Pp
+.Sh SYSCTL VARIABLES
+The following variables are available via
+.Xr sysctl 8 ,
+and as
+.Xr loader 8
+tunables:
+.Bl -tag -width indent
+.It Va dev.imx_spi.%d.debug
+Output debugging info when non-zero.
+A value of 1 displays information about bus transfers,
+2 adds information about bus clock frequency and chip select activity,
+and 3 adds information about interrupt handling.
+.El
+.Sh SEE ALSO
+.Xr fdt 4 ,
+.Xr fdt_pinctrl 4 ,
+.Xr sysctl 8
+.Sh HISTORY
+The
+.Nm
+driver first appeared in
+.Fx 12.0 .
diff --git a/static/freebsd/man4/man4.arm/imx_wdog.4 b/static/freebsd/man4/man4.arm/imx_wdog.4
new file mode 100644
index 00000000..cb4d0e13
--- /dev/null
+++ b/static/freebsd/man4/man4.arm/imx_wdog.4
@@ -0,0 +1,110 @@
+.\"
+.\" Copyright (c) 2018 Ian Lepore <ian@freebsd.org>
+.\" All rights reserved.
+.\"
+.\" Redistribution and use in source and binary forms, with or without
+.\" modification, are permitted provided that the following conditions
+.\" are met:
+.\"
+.\" 1. Redistributions of source code must retain the above copyright
+.\"    notice, this list of conditions and the following disclaimer.
+.\" 2. Redistributions in binary form must reproduce the above copyright
+.\"    notice, this list of conditions and the following disclaimer in the
+.\"    documentation and/or other materials provided with the distribution.
+.\"
+.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+.\" IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+.\" OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+.\" IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+.\" INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+.\" NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+.\" DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+.\" THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+.\" (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+.\" THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+.\"
+.Dd July 7, 2018
+.Dt IMX_WDOG 4 arm
+.Os
+.Sh NAME
+.Nm imx_wdog
+.Nd device driver for the NXP i.MX5 and i.MX6 watchdog timer
+.Sh SYNOPSIS
+To compile this driver into the kernel,
+place the following line in your
+kernel configuration file:
+.Bd -ragged -offset indent
+.Cd "device imxwdt"
+.Ed
+.Pp
+Alternatively, to load the driver as a
+module at boot time, place the following line in
+.Xr loader.conf 5 :
+.Bd -literal -offset indent
+imx_wdog_load="YES"
+.Ed
+.Sh DESCRIPTION
+The
+.Nm
+driver provides
+.Xr watchdog 4
+support for the watchdog timer present on NXP i.MX5 and i.MX6 processors.
+The i.MX watchdog hardware supports programmable timeouts ranging from
+0.5 to 128 seconds, in half-second increments.
+Once activated, the watchdog hardware cannot be deactivated, but the
+timeout period can be changed to any valid non-zero value.
+.Pp
+At power-on, a special 16-second
+.Sq power-down timer
+mode is automatically enabled by the hardware.
+It will assert the external WDOG_B signal, which may be connected to
+external hardware that causes the system to reset or power-down.
+The power-down timer is often reset by the boot loader (typically U-Boot).
+If the power-down timer is still active at the time when the normal
+watchdog is first enabled, the
+.Nm
+driver automatically disables it.
+.Pp
+The
+.Nm
+driver supports the FDT
+.Va fsl,external-reset
+property by enabling the assertion of the WDOG_B external timeout signal
+when the property is present.
+When running this way, the need to reset the system due to watchdog
+timeout is signaled by driving the WDOG_B line low; some external
+entity is expected to assert the chip's POR pin in response.
+The
+.Nm
+driver attempts to backstop this external reset by scheduling an
+interrupt to occur as well.
+The interrupt handler waits 1 second for the external reset to occur,
+then it triggers a normal software reset.
+Note that the WDOG_B signal can be configured to use a variety of
+pins on the chip.
+For the
+.Va fsl,external-reset
+property to be effective, the signal must be connected to an appropriate
+pin by the system's FDT pinctrl data.
+.Pp
+The
+.Nm
+driver supports the FDT
+.Va timeout-secs
+property by enabling the watchdog as soon as the driver attaches,
+using the given timeout value.
+This extends watchdog protection to much of the system startup process,
+but it still requires that
+.Xr watchdogd 4
+be configured to service the watchdog.
+.Sh SEE ALSO
+.Xr fdt 4 ,
+.Xr watchdog 4 ,
+.Xr watchdog 8 ,
+.Xr watchdogd 8 ,
+.Xr watchdog 9
+.Sh HISTORY
+The
+.Nm
+driver first appeared in
+.Fx 10.0 .
diff --git a/static/freebsd/man4/man4.arm/mge.4 b/static/freebsd/man4/man4.arm/mge.4
new file mode 100644
index 00000000..cba9327e
--- /dev/null
+++ b/static/freebsd/man4/man4.arm/mge.4
@@ -0,0 +1,158 @@
+.\"
+.\" Copyright (c) 2008 Semihalf, Rafal Jaworowski
+.\"
+.\" All rights reserved.
+.\"
+.\" Redistribution and use in source and binary forms, with or without
+.\" modification, are permitted provided that the following conditions
+.\" are met:
+.\" 1. Redistributions of source code must retain the above copyright
+.\"    notice, this list of conditions and the following disclaimer.
+.\" 2. Redistributions in binary form must reproduce the above copyright
+.\"    notice, this list of conditions and the following disclaimer in the
+.\"    documentation and/or other materials provided with the distribution.
+.\"
+.\" THIS SOFTWARE IS PROVIDED BY THE DEVELOPERS ``AS IS'' AND ANY EXPRESS OR
+.\" IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+.\" OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+.\" IN NO EVENT SHALL THE DEVELOPERS BE LIABLE FOR ANY DIRECT, INDIRECT,
+.\" INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+.\" NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+.\" DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+.\" THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+.\" (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+.\" THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+.\"
+.Dd November 27, 2008
+.Dt MGE 4 arm
+.Os
+.Sh NAME
+.Nm mge
+.Nd "Marvell Gigabit Ethernet device driver"
+.Sh SYNOPSIS
+To compile this driver into the kernel, place the following lines in your
+kernel configuration file:
+.Bd -ragged -offset indent
+.Cd "device mge"
+.Cd "device miibus"
+.Ed
+.Sh DESCRIPTION
+The
+.Nm
+driver provides support for gigabit Ethernet controller integrated in Marvell
+system-on-chip devices.
+.Pp
+The
+.Nm
+driver supports the following media types:
+.Bl -tag -width xxxxxxxxxxxxxxxxxxxx
+.It autoselect
+Enable autoselection of the media type and options
+.It 10baseT/UTP
+Set 10Mbps operation
+.It 100baseTX
+Set 100Mbps operation
+.It 1000baseT
+Set 1000baseT operation
+.El
+.Pp
+The
+.Nm
+driver supports the following media options:
+.Bl -tag -width xxxxxxxxxxxxxxxxxxxx
+.It full-duplex
+Set full duplex operation
+.El
+.Pp
+The
+.Nm
+driver supports polled operation when the system is configured with
+DEVICE_POLLING kernel option, see
+.Xr polling 4
+for more details.
+.Pp
+The
+.Nm
+driver supports reception and transmission of extended frames
+for
+.Xr vlan 4 .
+This capability of
+.Nm
+can be controlled by means of the
+.Cm vlanmtu
+parameter
+to
+.Xr ifconfig 8 .
+.Pp
+The
+.Nm
+driver supports interrupts coalescing (IC) so that raising a transmit/receive
+frame interrupt is delayed, if possible, until a threshold-defined period of
+time has elapsed.
+The following sysctls regulate this behaviour (separately for each path):
+.Bl -tag -width indent
+.It Va dev.mge.X.int_coal.rx_time
+.It Va dev.mge.X.int_coal.tx_time
+.Pp
+Value of 0 disables IC on the given path, value greater than zero corresponds
+to a real time period and is expressed in units equivalent to 64 ticks of the
+MGE clock.
+Maximum allowed value depends on MGE hardware revision.
+User provided values larger than supported will be trimmed to the maximum
+supported.
+More details are available in the reference manual of the device.
+.El
+.Sh HARDWARE
+Gigabit Ethernet controllers built into the following Marvell systems-on-chip
+are known to work with the
+.Nm
+driver:
+.Pp
+.Bl -bullet -compact
+.It
+Orion 88F5182
+.It
+Orion 88F5281
+.It
+Kirkwood 88F6281 (MGE V2)
+.It
+Discovery MV78100 (MGE V2)
+.El
+.Pp
+There are also Marvell system controllers for PowerPC processors, which
+include a variation of this gigabit Ethernet module integrated on chip, and
+they should also work with the
+.Nm
+driver, but this wasn't tested:
+.Pp
+.Bl -bullet -compact
+.It
+MV64430
+.It
+MV64460, MV64461, MV64462
+.El
+.Sh SEE ALSO
+.Xr altq 4 ,
+.Xr arp 4 ,
+.Xr miibus 4 ,
+.Xr netintro 4 ,
+.Xr ng_ether 4 ,
+.Xr polling 4 ,
+.Xr vlan 4 ,
+.Xr ifconfig 8
+.Sh HISTORY
+The
+.Nm
+device driver first appeared in
+.Fx 8.0 .
+.Sh AUTHORS
+.An -nosplit
+The base version of
+.Nm
+device driver was written by
+.An Grzegorz Bernacki.
+It has been extended with advanced features (polling, interrupt coalescing,
+multicast, h/w checksum calculation etc.) by
+.An Piotr Ziecik .
+This manual page was written by
+.An Rafal Jaworowski .
diff --git a/static/freebsd/man4/man4.arm/ti_adc.4 b/static/freebsd/man4/man4.arm/ti_adc.4
new file mode 100644
index 00000000..fb59e1d3
--- /dev/null
+++ b/static/freebsd/man4/man4.arm/ti_adc.4
@@ -0,0 +1,126 @@
+.\"
+.\" Copyright (c) 2014 Luiz Otavio O Souza <loos@freebsd.org>
+.\" All rights reserved.
+.\"
+.\" Redistribution and use in source and binary forms, with or without
+.\" modification, are permitted provided that the following conditions
+.\" are met:
+.\" 1. Redistributions of source code must retain the above copyright
+.\"    notice, this list of conditions and the following disclaimer.
+.\" 2. Redistributions in binary form must reproduce the above copyright
+.\"    notice, this list of conditions and the following disclaimer in the
+.\"    documentation and/or other materials provided with the distribution.
+.\"
+.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+.\" IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+.\" OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+.\" IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+.\" INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+.\" NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+.\" DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+.\" THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+.\" (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+.\" THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+.\"
+.Dd June 1, 2014
+.Dt TI_ADC 4 arm
+.Os
+.Sh NAME
+.Nm ti_adc
+.Nd TI AM3XXX analog to digital converter driver
+.Sh SYNOPSIS
+.Cd "device ti_adc"
+.Sh DESCRIPTION
+The
+.Nm
+driver provides access to the AIN (analog inputs) on am3xxx SoCs.
+.Pp
+It provides raw readings of the converted values for each analog inputs.
+.Pp
+The access to
+.Nm
+data is made via the
+.Xr sysctl 8
+interface:
+.Bd -literal
+dev.ti_adc.0.%desc: TI ADC controller
+dev.ti_adc.0.%driver: ti_adc
+dev.ti_adc.0.%pnpinfo: name=adc@44E0D000 compat=ti,adc
+dev.ti_adc.0.%parent: simplebus0
+dev.ti_adc.0.clockdiv: 2400
+dev.ti_adc.0.ain.0.enable: 0
+dev.ti_adc.0.ain.0.open_delay: 0
+dev.ti_adc.0.ain.0.samples_avg: 0
+dev.ti_adc.0.ain.0.input: 0
+dev.ti_adc.0.ain.1.enable: 0
+dev.ti_adc.0.ain.1.open_delay: 0
+dev.ti_adc.0.ain.1.samples_avg: 0
+dev.ti_adc.0.ain.1.input: 0
+dev.ti_adc.0.ain.2.enable: 0
+dev.ti_adc.0.ain.2.open_delay: 0
+dev.ti_adc.0.ain.2.samples_avg: 0
+dev.ti_adc.0.ain.2.input: 0
+dev.ti_adc.0.ain.3.enable: 0
+dev.ti_adc.0.ain.3.open_delay: 0
+dev.ti_adc.0.ain.3.samples_avg: 0
+dev.ti_adc.0.ain.3.input: 0
+dev.ti_adc.0.ain.4.enable: 0
+dev.ti_adc.0.ain.4.open_delay: 0
+dev.ti_adc.0.ain.4.samples_avg: 0
+dev.ti_adc.0.ain.4.input: 0
+dev.ti_adc.0.ain.5.enable: 0
+dev.ti_adc.0.ain.5.open_delay: 0
+dev.ti_adc.0.ain.5.samples_avg: 0
+dev.ti_adc.0.ain.5.input: 0
+dev.ti_adc.0.ain.6.enable: 1
+dev.ti_adc.0.ain.6.open_delay: 0
+dev.ti_adc.0.ain.6.samples_avg: 4
+dev.ti_adc.0.ain.6.input: 2308
+dev.ti_adc.0.ain.7.enable: 1
+dev.ti_adc.0.ain.7.open_delay: 0
+dev.ti_adc.0.ain.7.samples_avg: 0
+dev.ti_adc.0.ain.7.input: 3812
+.Ed
+.Pp
+On Beaglebone-black the analog input 7 is connected to the 3V3B rail through
+a voltage divisor (2:1).
+The 3V3B voltage rail comes from the TL5209 LDO regulator which is limited
+to 500mA maximum.
+.Pp
+Global settings:
+.Bl -tag -width ".Va dev.ti_adc.0.clockdiv"
+.It Va dev.ti_adc.0.clockdiv
+Sets the ADC clock prescaler.
+The minimum value is 10 and the maximum is 65535.
+The ADC clock is based on CLK_M_OSC (24Mhz) / clockdiv.
+This gives a maximum of ~2.4Mhz for the ADC clock and ~10Khz for the default
+setting (clockdiv = 2400).
+.El
+.Pp
+Settings per input:
+.Bl -tag -width ".Va dev.ti_adc.0.ain.%d.samples_avg"
+.It Va dev.ti_adc.0.ain.%d.enable
+Enable the conversion for the input.
+Each input should be individually enabled before it can be used.
+When all the inputs are disabled, the ADC is turned off.
+.It Va dev.ti_adc.0.ain.%d.open_delay
+Sets the number of ADC clock cycles to wait after applying the input
+configuration and before start the ADC conversion.
+.It Va dev.ti_adc.0.ain.%d.samples_avg
+Sets the number of samples average used on each input, it can be set to 0
+(no samples average), 2, 4, 8, or 16.
+.It Va dev.ti_adc.0.ain.%d.input
+Is the converted raw value of the voltage applied on the analog input.
+It is made of a 12 bit value (0 ~ 4095).
+.El
+.Sh SEE ALSO
+.Xr sysctl 8
+.Sh HISTORY
+The
+.Nm
+driver first appeared in
+.Fx 10.1 .
+.Sh AUTHORS
+.An -nosplit
+The driver and this manual page was written by
+.An Luiz Otavio O Souza Aq Mt loos@FreeBSD.org .