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#include "asm.hpp"
#include <cstdint>
#include <map>
#include <string>
#include "opcode.hpp"
namespace {
const std::map<std::string, instruction_t> instructions = {
{"lui", instruction_t{u_type{0, 0, opcode::LUI}} },
{"auipc", instruction_t{u_type{0, 0, opcode::AUIPC}} },
{"jal", instruction_t{j_type{0, 0, 0, 0, 0, opcode::JAL}} },
{"jalr", instruction_t{i_type{0, 0, 0b000, 0, opcode::JALR}} },
{"beq", instruction_t{b_type{0, 0, 0, 0, 0b000, 0, 0, opcode::BRANCH}} },
{"bne", instruction_t{b_type{0, 0, 0, 0, 0b001, 0, 0, opcode::BRANCH}} },
{"blt", instruction_t{b_type{0, 0, 0, 0, 0b100, 0, 0, opcode::BRANCH}} },
{"bge", instruction_t{b_type{0, 0, 0, 0, 0b101, 0, 0, opcode::BRANCH}} },
{"bltu", instruction_t{b_type{0, 0, 0, 0, 0b110, 0, 0, opcode::BRANCH}} },
{"bgeu", instruction_t{b_type{0, 0, 0, 0, 0b111, 0, 0, opcode::BRANCH}} },
{"lb", instruction_t{i_type{0, 0, 0b000, 0, opcode::LOAD}} },
{"lh", instruction_t{i_type{0, 0, 0b001, 0, opcode::LOAD}} },
{"lw", instruction_t{i_type{0, 0, 0b010, 0, opcode::LOAD}} },
{"lbu", instruction_t{i_type{0, 0, 0b100, 0, opcode::LOAD}} },
{"lhu", instruction_t{i_type{0, 0, 0b101, 0, opcode::LOAD}} },
{"sb", instruction_t{s_type{0, 0, 0, 0b000, 0, opcode::STORE}} },
{"sh", instruction_t{s_type{0, 0, 0, 0b001, 0, opcode::STORE}} },
{"sw", instruction_t{s_type{0, 0, 0, 0b010, 0, opcode::STORE}} },
{"addi", instruction_t{i_type{0, 0, 0b000, 0, opcode::OP_IMM}} },
{"slti", instruction_t{i_type{0, 0, 0b010, 0, opcode::OP_IMM}} },
{"sltiu", instruction_t{i_type{0, 0, 0b011, 0, opcode::OP_IMM}} },
{"xori", instruction_t{i_type{0, 0, 0b100, 0, opcode::OP_IMM}} },
{"ori", instruction_t{i_type{0, 0, 0b110, 0, opcode::OP_IMM}} },
{"andi", instruction_t{i_type{0, 0, 0b111, 0, opcode::OP_IMM}} },
{"slli", instruction_t{i_shift_type{0b000000, 0, 0, 0b001, 0, opcode::OP_IMM}} },
{"srli", instruction_t{i_shift_type{0b000000, 0, 0, 0b101, 0, opcode::OP_IMM}} },
{"srai", instruction_t{i_shift_type{0b010000, 0, 0, 0b101, 0, opcode::OP_IMM}} },
{"add", instruction_t{r_type{0b0000000, 0, 0, 0b000, 0, opcode::OP}} },
{"sub", instruction_t{r_type{0b0100000, 0, 0, 0b000, 0, opcode::OP}} },
{"sll", instruction_t{r_type{0b0000000, 0, 0, 0b001, 0, opcode::OP}} },
{"slt", instruction_t{r_type{0b0000000, 0, 0, 0b010, 0, opcode::OP}} },
{"sltu", instruction_t{r_type{0b0000000, 0, 0, 0b011, 0, opcode::OP}} },
{"xor", instruction_t{r_type{0b0000000, 0, 0, 0b100, 0, opcode::OP}} },
{"srl", instruction_t{r_type{0b0000000, 0, 0, 0b101, 0, opcode::OP}} },
{"sra", instruction_t{r_type{0b0100000, 0, 0, 0b101, 0, opcode::OP}} },
{"or", instruction_t{r_type{0b0000000, 0, 0, 0b110, 0, opcode::OP}} },
{"and", instruction_t{r_type{0b0000000, 0, 0, 0b111, 0, opcode::OP}} },
{"fence", instruction_t{i_type{0, 0, 0b000, 0, opcode::MISC_MEM}} },
{"ecall", instruction_t{i_type{0b000000000000, 0, 0b000, 0, opcode::SYSTEM}} },
{"ebreak", instruction_t{i_type{0b000000000001, 0, 0b000, 0, opcode::SYSTEM}} },
{"addiw", instruction_t{i_type{0, 0, 0b000, 0, opcode::OP_IMM_32}} },
{"slliw", instruction_t{i_shift_type{0b000000, 0, 0, 0b001, 0, opcode::OP_IMM_32}}},
{"srliw", instruction_t{i_shift_type{0b000000, 0, 0, 0b101, 0, opcode::OP_IMM_32}}},
{"sraiw", instruction_t{i_shift_type{0b010000, 0, 0, 0b101, 0, opcode::OP_IMM_32}}},
{"addw", instruction_t{r_type{0b0000000, 0, 0, 0b000, 0, opcode::OP_32}} },
{"subw", instruction_t{r_type{0b0100000, 0, 0, 0b000, 0, opcode::OP_32}} },
{"sllw", instruction_t{r_type{0b0000000, 0, 0, 0b001, 0, opcode::OP_32}} },
{"srlw", instruction_t{r_type{0b0000000, 0, 0, 0b101, 0, opcode::OP_32}} },
{"sraw", instruction_t{r_type{0b0100000, 0, 0, 0b101, 0, opcode::OP_32}} },
{"ld", instruction_t{i_type{0, 0, 0b011, 0, opcode::LOAD}} },
{"lwu", instruction_t{i_type{0, 0, 0b110, 0, opcode::LOAD}} },
{"sd", instruction_t{s_type{0, 0, 0, 0b011, 0, opcode::STORE}} },
{"mul", instruction_t{r_type{0b0000001, 0, 0, 0b000, 0, opcode::OP}} },
{"mulh", instruction_t{r_type{0b0000001, 0, 0, 0b001, 0, opcode::OP}} },
{"mulhsu", instruction_t{r_type{0b0000001, 0, 0, 0b010, 0, opcode::OP}} },
{"mulhu", instruction_t{r_type{0b0000001, 0, 0, 0b011, 0, opcode::OP}} },
{"div", instruction_t{r_type{0b0000001, 0, 0, 0b100, 0, opcode::OP}} },
{"divu", instruction_t{r_type{0b0000001, 0, 0, 0b101, 0, opcode::OP}} },
{"rem", instruction_t{r_type{0b0000001, 0, 0, 0b110, 0, opcode::OP}} },
{"remu", instruction_t{r_type{0b0000001, 0, 0, 0b111, 0, opcode::OP}} },
{"mulw", instruction_t{r_type{0b0000001, 0, 0, 0b000, 0, opcode::OP_32}} },
{"divw", instruction_t{r_type{0b0000001, 0, 0, 0b100, 0, opcode::OP_32}} },
{"divuw", instruction_t{r_type{0b0000001, 0, 0, 0b101, 0, opcode::OP_32}} },
{"remw", instruction_t{r_type{0b0000001, 0, 0, 0b110, 0, opcode::OP_32}} },
{"remuw", instruction_t{r_type{0b0000001, 0, 0, 0b111, 0, opcode::OP_32}} },
};
const std::map<std::string, uint8_t> registers = {
{"x0", 0 },
{"x1", 1 },
{"x2", 2 },
{"x3", 3 },
{"x4", 4 },
{"x5", 5 },
{"x6", 6 },
{"x7", 7 },
{"x8", 8 },
{"x9", 9 },
{"x10", 10},
{"x11", 11},
{"x12", 12},
{"x13", 13},
{"x14", 14},
{"x15", 15},
{"x16", 16},
{"x17", 17},
{"x18", 18},
{"x19", 19},
{"x20", 20},
{"x21", 21},
{"x22", 22},
{"x23", 23},
{"x24", 24},
{"x25", 25},
{"x26", 26},
{"x27", 27},
{"x28", 28},
{"x29", 29},
{"x30", 30},
{"x31", 31},
{"zero", 0 },
{"ra", 1 },
{"sp", 2 },
{"gp", 3 },
{"tp", 4 },
{"t0", 5 },
{"t1", 6 },
{"t2", 7 },
{"s0", 8 },
{"fp", 8 },
{"s1", 9 },
{"a0", 10},
{"a1", 11},
{"a2", 12},
{"a3", 13},
{"a4", 14},
{"a5", 15},
{"a6", 16},
{"a7", 17},
{"s2", 18},
{"s3", 19},
{"s4", 20},
{"s5", 21},
{"s6", 22},
{"s7", 23},
{"s8", 24},
{"s9", 25},
{"s10", 26},
{"s11", 27},
{"t3", 28},
{"t4", 29},
{"t5", 30},
{"t6", 31},
};
} // namespace
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