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diff --git a/static/freebsd/man4/cxgbe.4 3.html b/static/freebsd/man4/cxgbe.4 3.html new file mode 100644 index 00000000..96010d56 --- /dev/null +++ b/static/freebsd/man4/cxgbe.4 3.html @@ -0,0 +1,382 @@ +<table class="head"> + <tr> + <td class="head-ltitle">CXGBE(4)</td> + <td class="head-vol">Device Drivers Manual</td> + <td class="head-rtitle">CXGBE(4)</td> + </tr> +</table> +<div class="manual-text"> +<section class="Sh"> +<h1 class="Sh" id="NAME"><a class="permalink" href="#NAME">NAME</a></h1> +<p class="Pp"><code class="Nm">cxgbe</code> — <span class="Nd">Chelsio + T7, T6, T5, and T4 based 1Gb to 400Gb Ethernet driver</span></p> +</section> +<section class="Sh"> +<h1 class="Sh" id="SYNOPSIS"><a class="permalink" href="#SYNOPSIS">SYNOPSIS</a></h1> +<p class="Pp">To compile this driver into the kernel, place the following lines + in your kernel configuration file:</p> +<div class="Bd Pp Bd-indent"><code class="Cd">device cxgbe</code></div> +<p class="Pp">To load the driver as a module at boot time, place the following + lines in <a class="Xr">loader.conf(5)</a>:</p> +<div class="Bd Pp Bd-indent Li"> +<pre>t7fw_cfg_load="YES" +t6fw_cfg_load="YES" +t5fw_cfg_load="YES" +t4fw_cfg_load="YES" +if_cxgbe_load="YES"</pre> +</div> +</section> +<section class="Sh"> +<h1 class="Sh" id="DESCRIPTION"><a class="permalink" href="#DESCRIPTION">DESCRIPTION</a></h1> +<p class="Pp">The <code class="Nm">cxgbe</code> driver provides support for PCI + Express Ethernet adapters based on the Chelsio Terminator 7, Terminator 6, + Terminator 5, and Terminator 4 ASICs (T7, T6, T5, and T4). The driver + supports Jumbo Frames, Transmit/Receive checksum offload, TCP segmentation + offload (TSO), Large Receive Offload (LRO), VLAN tag insertion/extraction, + VLAN checksum offload, VLAN TSO, VXLAN checksum offload, VXLAN TSO, and + Receive Side Steering (RSS). For further hardware information and questions + related to hardware requirements, see + <span class="Pa">http://www.chelsio.com/</span>.</p> +<p class="Pp">The <code class="Nm">cxgbe</code> driver uses different names for + devices based on the associated ASIC:</p> +<table class="Bl-column Bd-indent"> + <tr id="ASIC"> + <td><a class="permalink" href="#ASIC"><b class="Sy">ASIC</b></a></td> + <td><a class="permalink" href="#Port"><b class="Sy" id="Port">Port + Name</b></a></td> + <td><a class="permalink" href="#Parent"><b class="Sy" id="Parent">Parent + Device</b></a></td> + <td><a class="permalink" href="#Virtual"><b class="Sy" id="Virtual">Virtual + Interface</b></a></td> + </tr> + <tr> + <td>T7</td> + <td>che</td> + <td>chnex</td> + <td>vche</td> + </tr> + <tr> + <td>T6</td> + <td>cc</td> + <td>t6nex</td> + <td>vcc</td> + </tr> + <tr> + <td>T5</td> + <td>cxl</td> + <td>t5nex</td> + <td>vcxl</td> + </tr> + <tr> + <td>T4</td> + <td>cxgbe</td> + <td>t4nex</td> + <td>vcxgbe</td> + </tr> +</table> +<p class="Pp">Loader tunables with the hw.cxgbe prefix apply to all cards. The + driver provides sysctl MIBs for both ports and parent devices using the + names above. For example, a T5 adapter provides port MIBs under dev.cxl and + adapter-wide MIBs under dev.t5nex. References to sysctl MIBs in the + remainder of this page use dev.<port> for port MIBs and + dev.<nexus> for adapter-wide MIBs.</p> +<p class="Pp">For more information on configuring this device, see + <a class="Xr">ifconfig(8)</a>.</p> +</section> +<section class="Sh"> +<h1 class="Sh" id="HARDWARE"><a class="permalink" href="#HARDWARE">HARDWARE</a></h1> +<p class="Pp">The <code class="Nm">cxgbe</code> driver supports 400Gb, 200Gb, + 50Gb, and 10Gb Ethernet adapters based on the T7 ASIC:</p> +<p class="Pp"></p> +<ul class="Bl-bullet Bl-compact"> + <li>Chelsio S71400</li> + <li>Chelsio S72200</li> + <li>Chelsio S72200-OCP</li> + <li>Chelsio T72200</li> + <li>Chelsio T72200-DPU</li> + <li>Chelsio T72200-FH</li> + <li>Chelsio T72200-FH-DPU</li> + <li>Chelsio T72200-OCP</li> + <li>Chelsio S7450-DPU</li> + <li>Chelsio S7450-OCP</li> + <li>Chelsio T71200-iNIC</li> + <li>Chelsio T7250</li> + <li>Chelsio T7210-BT</li> + <li>Chelsio T7410-BT-OCP</li> +</ul> +<p class="Pp">The <code class="Nm">cxgbe</code> driver supports 100Gb and 25Gb + Ethernet adapters based on the T6 ASIC:</p> +<p class="Pp"></p> +<ul class="Bl-bullet Bl-compact"> + <li>Chelsio T6225-CR</li> + <li>Chelsio T6225-SO-CR</li> + <li>Chelsio T62100-LP-CR</li> + <li>Chelsio T62100-SO-CR</li> + <li>Chelsio T62100-CR</li> +</ul> +<p class="Pp">The <code class="Nm">cxgbe</code> driver supports 40Gb, 10Gb and + 1Gb Ethernet adapters based on the T5 ASIC:</p> +<p class="Pp"></p> +<ul class="Bl-bullet Bl-compact"> + <li>Chelsio T580-CR</li> + <li>Chelsio T580-LP-CR</li> + <li>Chelsio T580-LP-SO-CR</li> + <li>Chelsio T560-CR</li> + <li>Chelsio T540-CR</li> + <li>Chelsio T540-LP-CR</li> + <li>Chelsio T522-CR</li> + <li>Chelsio T520-LL-CR</li> + <li>Chelsio T520-CR</li> + <li>Chelsio T520-SO</li> + <li>Chelsio T520-BT</li> + <li>Chelsio T504-BT</li> +</ul> +<p class="Pp">The <code class="Nm">cxgbe</code> driver supports 10Gb and 1Gb + Ethernet adapters based on the T4 ASIC:</p> +<p class="Pp"></p> +<ul class="Bl-bullet Bl-compact"> + <li>Chelsio T420-CR</li> + <li>Chelsio T422-CR</li> + <li>Chelsio T440-CR</li> + <li>Chelsio T420-BCH</li> + <li>Chelsio T440-BCH</li> + <li>Chelsio T440-CH</li> + <li>Chelsio T420-SO</li> + <li>Chelsio T420-CX</li> + <li>Chelsio T420-BT</li> + <li>Chelsio T404-BT</li> +</ul> +</section> +<section class="Sh"> +<h1 class="Sh" id="LOADER_TUNABLES"><a class="permalink" href="#LOADER_TUNABLES">LOADER + TUNABLES</a></h1> +<p class="Pp">Tunables can be set at the <a class="Xr">loader(8)</a> prompt + before booting the kernel or stored in <a class="Xr">loader.conf(5)</a>. + There are multiple tunables that control the number of queues of various + types. A negative value for such a tunable instructs the driver to create up + to that many queues if there are enough CPU cores available.</p> +<dl class="Bl-tag"> + <dt id="hw.cxgbe.ntxq"><var class="Va">hw.cxgbe.ntxq</var></dt> + <dd>Number of NIC tx queues used for a port. The default is 16 or the number + of CPU cores in the system, whichever is less.</dd> + <dt id="hw.cxgbe.nrxq"><var class="Va">hw.cxgbe.nrxq</var></dt> + <dd>Number of NIC rx queues used for a port. The default is 8 or the number of + CPU cores in the system, whichever is less.</dd> + <dt id="hw.cxgbe.nofldtxq"><var class="Va">hw.cxgbe.nofldtxq</var></dt> + <dd>Number of TOE tx queues used for a port. The default is 8 or the number of + CPU cores in the system, whichever is less.</dd> + <dt id="hw.cxgbe.nofldrxq"><var class="Va">hw.cxgbe.nofldrxq</var></dt> + <dd>Number of TOE rx queues used for a port. The default is 2 or the number of + CPU cores in the system, whichever is less.</dd> + <dt id="hw.cxgbe.num_vis"><var class="Va">hw.cxgbe.num_vis</var></dt> + <dd>Number of virtual interfaces (VIs) created for each port. Each virtual + interface creates a separate network interface. The first virtual + interface on each port is required and represents the primary network + interface on the port. Additional virtual interfaces on a port are named + using the Virtual Interface name from the table above. Additional virtual + interfaces use a single pair of queues for rx and tx as well an additional + pair of queues for TOE rx and tx. The default is 1.</dd> + <dt id="hw.cxgbe.holdoff_timer_idx"><var class="Va">hw.cxgbe.holdoff_timer_idx</var></dt> + <dd style="width: auto;"> </dd> + <dt id="hw.cxgbe.holdoff_timer_idx_ofld"><var class="Va">hw.cxgbe.holdoff_timer_idx_ofld</var></dt> + <dd>Timer index value used to delay interrupts. The holdoff timer list has the + values 1, 5, 10, 50, 100, and 200 by default (all values are in + microseconds) and the index selects a value from this list. + holdoff_timer_idx_ofld applies to queues used for TOE rx. The default + value is 1 which means the timer value is 5us. Different interfaces can be + assigned different values at any time via the + dev.<port>.X.holdoff_tmr_idx and + dev.<port>.X.holdoff_tmr_idx_ofld sysctls.</dd> + <dt id="hw.cxgbe.holdoff_pktc_idx"><var class="Va">hw.cxgbe.holdoff_pktc_idx</var></dt> + <dd style="width: auto;"> </dd> + <dt id="hw.cxgbe.holdoff_pktc_idx_ofld"><var class="Va">hw.cxgbe.holdoff_pktc_idx_ofld</var></dt> + <dd>Packet-count index value used to delay interrupts. The packet-count list + has the values 1, 8, 16, and 32 by default, and the index selects a value + from this list. holdoff_pktc_idx_ofld applies to queues used for TOE rx. + The default value is -1 which means packet counting is disabled and + interrupts are generated based solely on the holdoff timer value. + Different interfaces can be assigned different values via the + dev.<port>.X.holdoff_pktc_idx and + dev.<port>.X.holdoff_pktc_idx_ofld sysctls. These sysctls work only + when the interface has never been marked up (as done by ifconfig up).</dd> + <dt id="hw.cxgbe.qsize_txq"><var class="Va">hw.cxgbe.qsize_txq</var></dt> + <dd>Number of entries in a transmit queue's descriptor ring. A buf_ring of the + same size is also allocated for additional software queuing. See + <a class="Xr">ifnet(9)</a>. The default value is 1024. Different + interfaces can be assigned different values via the + dev.<port>.X.qsize_txq sysctl. This sysctl works only when the + interface has never been marked up (as done by ifconfig up).</dd> + <dt id="hw.cxgbe.qsize_rxq"><var class="Va">hw.cxgbe.qsize_rxq</var></dt> + <dd>Number of entries in a receive queue's descriptor ring. The default value + is 1024. Different interfaces can be assigned different values via the + dev.<port>.X.qsize_rxq sysctl. This sysctl works only when the + interface has never been marked up (as done by ifconfig up).</dd> + <dt id="hw.cxgbe.interrupt_types"><var class="Va">hw.cxgbe.interrupt_types</var></dt> + <dd>Permitted interrupt types. Bit 0 represents INTx (line interrupts), bit 1 + MSI, and bit 2 MSI-X. The default is 7 (all allowed). The driver selects + the best possible type out of the allowed types.</dd> + <dt id="hw.cxgbe.pcie_relaxed_ordering"><var class="Va">hw.cxgbe.pcie_relaxed_ordering</var></dt> + <dd>PCIe Relaxed Ordering. -1 indicates the driver should determine whether to + enable or disable PCIe RO. 0 disables PCIe RO. 1 enables PCIe RO. 2 + indicates the driver should not modify the PCIe RO setting. The default is + -1.</dd> + <dt id="hw.cxgbe.fw_install"><var class="Va">hw.cxgbe.fw_install</var></dt> + <dd>0 prohibits the driver from installing a firmware on the card. 1 allows + the driver to install a new firmware if internal driver heuristics + indicate that the new firmware is preferable to the one already on the + card. 2 instructs the driver to always install the new firmware on the + card as long as it is compatible with the driver and is a different + version than the one already on the card. The default is 1.</dd> + <dt id="hw.cxgbe.fl_pktshift"><var class="Va">hw.cxgbe.fl_pktshift</var></dt> + <dd>Number of padding bytes inserted before the beginning of an Ethernet frame + in the receive buffer. The default value is 0. A value of 2 would ensure + that the Ethernet payload (usually the IP header) is at a 4 byte aligned + address. 0-7 are all valid values.</dd> + <dt id="hw.cxgbe.fl_pad"><var class="Va">hw.cxgbe.fl_pad</var></dt> + <dd>A non-zero value ensures that writes from the hardware to a receive buffer + are padded up to the specified boundary. The default is -1 which lets the + driver pick a pad boundary. 0 disables trailer padding completely.</dd> + <dt id="hw.cxgbe.cong_drop"><var class="Va">hw.cxgbe.cong_drop</var></dt> + <dd>Controls the hardware response to congestion. -1 disables congestion + feedback and is not recommended. 0 instructs the hardware to backpressure + its pipeline on congestion. This usually results in the port emitting + PAUSE frames. 1 instructs the hardware to drop frames destined for + congested queues. 2 instructs the hardware to both backpressure the + pipeline and drop frames.</dd> + <dt id="hw.cxgbe.pause_settings"><var class="Va">hw.cxgbe.pause_settings</var></dt> + <dd>PAUSE frame settings. Bit 0 is rx_pause, bit 1 is tx_pause, bit 2 is + pause_autoneg. rx_pause = 1 instructs the hardware to heed incoming PAUSE + frames, 0 instructs it to ignore them. tx_pause = 1 allows the hardware to + emit PAUSE frames when its receive FIFO reaches a high threshold, 0 + prohibits the hardware from emitting PAUSE frames. pause_autoneg = 1 + overrides the rx_pause and tx_pause bits and instructs the hardware to + negotiate PAUSE settings with the link peer. The default is 7 (all three = + 1). This tunable establishes the default PAUSE settings for all ports. + Settings can be displayed and controlled on a per-port basis via the + dev.<port>.X.pause_settings sysctl.</dd> + <dt id="hw.cxgbe.fec"><var class="Va">hw.cxgbe.fec</var></dt> + <dd>Forward Error Correction settings. -1 (default) means driver should + automatically pick a value. 0 disables FEC. Finer grained control can be + achieved by setting individual bits. Bit 0 enables RS FEC, bit 1 enables + BASE-R FEC (aka Firecode FEC), bit 2 enables NO FEC, and bit 6 enables the + FEC that is recommended by the transceiver/cable that is plugged in. These + bits can be set together in any combination. This tunable establishes the + default FEC settings for all ports. Settings can be controlled on a + per-port basis via the dev.<port>.X.requested_fec sysctl. The FEC in + use on the link is available in dev.<port>.X.link_fec when the link + is up.</dd> + <dt id="hw.cxgbe.autoneg"><var class="Va">hw.cxgbe.autoneg</var></dt> + <dd>Link autonegotiation settings. This tunable establishes the default + autonegotiation settings for all ports. Settings can be displayed and + controlled on a per-port basis via the dev.<port>.X.autoneg sysctl. + 0 disables autonegotiation. 1 enables autonegotiation. The default is -1 + which lets the driver pick a value. dev.<port>.X.autoneg is -1 for + port and module combinations that do not support autonegotiation.</dd> + <dt id="hw.cxgbe.buffer_packing"><var class="Va">hw.cxgbe.buffer_packing</var></dt> + <dd>Allow the hardware to deliver multiple frames in the same receive buffer + opportunistically. The default is -1 which lets the driver decide. 0 or 1 + explicitly disable or enable this feature.</dd> + <dt id="hw.cxgbe.largest_rx_cluster"><var class="Va">hw.cxgbe.largest_rx_cluster</var></dt> + <dd style="width: auto;"> </dd> + <dt id="hw.cxgbe.safest_rx_cluster"><var class="Va">hw.cxgbe.safest_rx_cluster</var></dt> + <dd>Sizes of rx clusters. Each of these must be set to one of the sizes + available (usually 2048, 4096, 9216, and 16384) and largest_rx_cluster + must be greater than or equal to safest_rx_cluster. The defaults are 16384 + and 4096 respectively. The driver never attempts to allocate a receive + buffer larger than largest_rx_cluster and falls back to allocating buffers + of safest_rx_cluster size if an allocation larger than safest_rx_cluster + fails. Note that largest_rx_cluster merely establishes a ceiling -- the + driver is allowed to allocate buffers of smaller sizes.</dd> + <dt id="hw.cxgbe.config_file"><var class="Va">hw.cxgbe.config_file</var></dt> + <dd>Select a pre-packaged device configuration file. A configuration file + contains a recipe for partitioning and configuring the hardware resources + on the card. This tunable is for specialized applications only and should + not be used in normal operation. The configuration profile currently in + use is available in the dev.<nexus>.X.cf and + dev.<nexus>.X.cfcsum sysctls.</dd> + <dt id="hw.cxgbe.linkcaps_allowed"><var class="Va">hw.cxgbe.linkcaps_allowed</var></dt> + <dd style="width: auto;"> </dd> + <dt id="hw.cxgbe.niccaps_allowed"><var class="Va">hw.cxgbe.niccaps_allowed</var></dt> + <dd style="width: auto;"> </dd> + <dt id="hw.cxgbe.toecaps_allowed"><var class="Va">hw.cxgbe.toecaps_allowed</var></dt> + <dd style="width: auto;"> </dd> + <dt id="hw.cxgbe.rdmacaps_allowed"><var class="Va">hw.cxgbe.rdmacaps_allowed</var></dt> + <dd style="width: auto;"> </dd> + <dt id="hw.cxgbe.iscsicaps_allowed"><var class="Va">hw.cxgbe.iscsicaps_allowed</var></dt> + <dd style="width: auto;"> </dd> + <dt id="hw.cxgbe.fcoecaps_allowed"><var class="Va">hw.cxgbe.fcoecaps_allowed</var></dt> + <dd>Disallowing capabilities provides a hint to the driver and firmware to not + reserve hardware resources for that feature. Each of these is a bit field + with a bit for each sub-capability within the capability. This tunable is + for specialized applications only and should not be used in normal + operation. The capabilities for which hardware resources have been + reserved are listed in dev.<nexus>.X.*caps sysctls.</dd> + <dt id="hw.cxgbe.tx_vm_wr"><var class="Va">hw.cxgbe.tx_vm_wr</var></dt> + <dd>Setting this to 1 instructs the driver to use VM work requests to transmit + data. This lets PF interfaces transmit frames to VF interfaces over the + internal switch in the ASIC. Note that the <a class="Xr">cxgbev(4)</a> VF + driver always uses VM work requests and is not affected by this tunable. + The default value is 0 and should be changed only if PF and VF interfaces + need to communicate with each other. Different interfaces can be assigned + different values using the dev.<port>.X.tx_vm_wr sysctl when the + interface is administratively down.</dd> + <dt id="hw.cxgbe.attack_filter"><var class="Va">hw.cxgbe.attack_filter</var></dt> + <dd>Set to 1 to enable the "attack filter". Default is 0. The attack + filter will drop an incoming frame if any of these conditions is true: src + ip/ip6 == dst ip/ip6; tcp and src/dst ip is not unicast; src/dst ip is + loopback (127.x.y.z); src ip6 is not unicast; src/dst ip6 is loopback + (::1/128) or unspecified (::/128); tcp and src/dst ip6 is mcast + (ff00::/8). This facility is available on T4 and T5 based cards only.</dd> + <dt id="hw.cxgbe.drop_ip_fragments"><var class="Va">hw.cxgbe.drop_ip_fragments</var></dt> + <dd>Set to 1 to drop all incoming IP fragments. Default is 0. Note that this + drops valid frames.</dd> + <dt id="hw.cxgbe.drop_pkts_with_l2_errors"><var class="Va">hw.cxgbe.drop_pkts_with_l2_errors</var></dt> + <dd>Set to 1 to drop incoming frames with Layer 2 length or checksum errors. + Default is 1.</dd> + <dt id="hw.cxgbe.drop_pkts_with_l3_errors"><var class="Va">hw.cxgbe.drop_pkts_with_l3_errors</var></dt> + <dd>Set to 1 to drop incoming frames with IP version, length, or checksum + errors. The IP checksum is validated for TCP or UDP packets only. Default + is 0.</dd> + <dt id="hw.cxgbe.drop_pkts_with_l4_errors"><var class="Va">hw.cxgbe.drop_pkts_with_l4_errors</var></dt> + <dd>Set to 1 to drop incoming frames with Layer 4 (TCP or UDP) length, + checksum, or other errors. Default is 0.</dd> +</dl> +</section> +<section class="Sh"> +<h1 class="Sh" id="SUPPORT"><a class="permalink" href="#SUPPORT">SUPPORT</a></h1> +<p class="Pp">For general information and support, go to the Chelsio support + website at: <span class="Pa">http://www.chelsio.com/</span>.</p> +<p class="Pp">If an issue is identified with this driver with a supported + adapter, email all the specific information related to the issue to + <<a class="Mt" href="mailto:support@chelsio.com">support@chelsio.com</a>>.</p> +</section> +<section class="Sh"> +<h1 class="Sh" id="SEE_ALSO"><a class="permalink" href="#SEE_ALSO">SEE + ALSO</a></h1> +<p class="Pp"><a class="Xr">arp(4)</a>, <a class="Xr">ccr(4)</a>, + <a class="Xr">cxgb(4)</a>, <a class="Xr">cxgbev(4)</a>, + <a class="Xr">netintro(4)</a>, <a class="Xr">ng_ether(4)</a>, + <a class="Xr">ifconfig(8)</a></p> +</section> +<section class="Sh"> +<h1 class="Sh" id="HISTORY"><a class="permalink" href="#HISTORY">HISTORY</a></h1> +<p class="Pp">The <code class="Nm">cxgbe</code> device driver first appeared in + <span class="Ux">FreeBSD 9.0</span>. Support for T5 cards first appeared in + <span class="Ux">FreeBSD 9.2</span> and <span class="Ux">FreeBSD + 10.0</span>. Support for T6 cards first appeared in <span class="Ux">FreeBSD + 11.1</span> and <span class="Ux">FreeBSD 12.0</span>. Support for T7 cards + first appeared in <span class="Ux">FreeBSD 15.0</span>.</p> +</section> +<section class="Sh"> +<h1 class="Sh" id="AUTHORS"><a class="permalink" href="#AUTHORS">AUTHORS</a></h1> +<p class="Pp">The <code class="Nm">cxgbe</code> driver was written by + <span class="An">Navdeep Parhar</span> + <<a class="Mt" href="mailto:np@FreeBSD.org">np@FreeBSD.org</a>>.</p> +</section> +</div> +<table class="foot"> + <tr> + <td class="foot-date">December 17, 2025</td> + <td class="foot-os">FreeBSD 15.0</td> + </tr> +</table> |