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diff --git a/static/freebsd/man4/ahc.4 3.html b/static/freebsd/man4/ahc.4 3.html new file mode 100644 index 00000000..919d48ce --- /dev/null +++ b/static/freebsd/man4/ahc.4 3.html @@ -0,0 +1,372 @@ +<table class="head"> + <tr> + <td class="head-ltitle">AHC(4)</td> + <td class="head-vol">Device Drivers Manual</td> + <td class="head-rtitle">AHC(4)</td> + </tr> +</table> +<div class="manual-text"> +<section class="Sh"> +<h1 class="Sh" id="NAME"><a class="permalink" href="#NAME">NAME</a></h1> +<p class="Pp"><code class="Nm">ahc</code> — <span class="Nd">Adaptec + VL/ISA/PCI SCSI host adapter driver</span></p> +</section> +<section class="Sh"> +<h1 class="Sh" id="SYNOPSIS"><a class="permalink" href="#SYNOPSIS">SYNOPSIS</a></h1> +<p class="Pp">To compile this driver into the kernel, place the following lines + in your kernel configuration file:</p> +<div class="Bd Pp Bd-indent"><code class="Cd">device scbus</code> +<br/> +<code class="Cd">device ahc</code> +<p class="Pp">For one or more PCI cards: + <br/> + <code class="Cd">device pci</code></p> +</div> +<p class="Pp">Alternatively, to load the driver as a module at boot time, place + the following lines in <a class="Xr">loader.conf(5)</a>:</p> +<div class="Bd Pp Bd-indent Li"> +<pre>ahc_load="YES" +ahc_isa_load="YES" +ahc_pci_load="YES"</pre> +</div> +</section> +<section class="Sh"> +<h1 class="Sh" id="DESCRIPTION"><a class="permalink" href="#DESCRIPTION">DESCRIPTION</a></h1> +<p class="Pp">This driver provides access to the SCSI bus(es) connected to the + Adaptec AIC77xx and AIC78xx host adapter chips.</p> +<p class="Pp">Driver features include support for twin and wide busses, fast, + ultra or ultra2 synchronous transfers depending on controller type, tagged + queueing, SCB paging, and target mode.</p> +<p class="Pp">Per target configuration performed in the SCSI-Select menu, + accessible at boot is honored by this driver. This includes + synchronous/asynchronous transfers, maximum synchronous negotiation rate, + wide transfers, disconnection, the host adapter's SCSI ID. For systems that + store non-volatile settings in a system specific manner rather than a serial + eeprom directly connected to the aic7xxx controller, the BIOS must be + enabled for the driver to access this information. This restriction applies + to many chip-down motherboard configurations.</p> +<p class="Pp">Performance and feature sets vary throughout the aic7xxx product + line. The following table provides a comparison of the different chips + supported by the <code class="Nm">ahc</code> driver. Note that wide and twin + channel features, although always supported by a particular chip, may be + disabled in a particular motherboard or card design.</p> +<div class="Bd Pp Bd-indent"> +<table class="Bl-column"> + <tr id="Chip"> + <td><a class="permalink" href="#Chip"><i class="Em">Chip</i></a></td> + <td>MIPS</td> + <td>Bus</td> + <td>MaxSync</td> + <td>MaxWidth</td> + <td>SCBs</td> + <td>Features</td> + </tr> + <tr> + <td>aic7770</td> + <td>10</td> + <td>VL</td> + <td>10MHz</td> + <td>16Bit</td> + <td>4</td> + <td>1</td> + </tr> + <tr> + <td>aic7850</td> + <td>10</td> + <td>PCI/32</td> + <td>10MHz</td> + <td>8Bit</td> + <td>3</td> + <td></td> + </tr> + <tr> + <td>aic7860</td> + <td>10</td> + <td>PCI/32</td> + <td>20MHz</td> + <td>8Bit</td> + <td>3</td> + <td></td> + </tr> + <tr> + <td>aic7870</td> + <td>10</td> + <td>PCI/32</td> + <td>10MHz</td> + <td>16Bit</td> + <td>16</td> + <td></td> + </tr> + <tr> + <td>aic7880</td> + <td>10</td> + <td>PCI/32</td> + <td>20MHz</td> + <td>16Bit</td> + <td>16</td> + <td></td> + </tr> + <tr> + <td>aic7890</td> + <td>20</td> + <td>PCI/32</td> + <td>40MHz</td> + <td>16Bit</td> + <td>16</td> + <td>3 4 5 6 7 8</td> + </tr> + <tr> + <td>aic7891</td> + <td>20</td> + <td>PCI/64</td> + <td>40MHz</td> + <td>16Bit</td> + <td>16</td> + <td>3 4 5 6 7 8</td> + </tr> + <tr> + <td>aic7892</td> + <td>20</td> + <td>PCI/64</td> + <td>80MHz</td> + <td>16Bit</td> + <td>16</td> + <td>3 4 5 6 7 8</td> + </tr> + <tr> + <td>aic7895</td> + <td>15</td> + <td>PCI/32</td> + <td>20MHz</td> + <td>16Bit</td> + <td>16</td> + <td>2 3 4 5</td> + </tr> + <tr> + <td>aic7895C</td> + <td>15</td> + <td>PCI/32</td> + <td>20MHz</td> + <td>16Bit</td> + <td>16</td> + <td>2 3 4 5 8</td> + </tr> + <tr> + <td>aic7896</td> + <td>20</td> + <td>PCI/32</td> + <td>40MHz</td> + <td>16Bit</td> + <td>16</td> + <td>2 3 4 5 6 7 8</td> + </tr> + <tr> + <td>aic7897</td> + <td>20</td> + <td>PCI/64</td> + <td>40MHz</td> + <td>16Bit</td> + <td>16</td> + <td>2 3 4 5 6 7 8</td> + </tr> + <tr> + <td>aic7899</td> + <td>20</td> + <td>PCI/64</td> + <td>80MHz</td> + <td>16Bit</td> + <td>16</td> + <td>2 3 4 5 6 7 8</td> + </tr> +</table> +<p class="Pp"></p> +<ol class="Bl-enum Bl-compact"> + <li>Multiplexed Twin Channel Device - One controller servicing two + busses.</li> + <li>Multi-function Twin Channel Device - Two controllers on one chip.</li> + <li>Command Channel Secondary DMA Engine - Allows scatter gather list and SCB + prefetch.</li> + <li>64 Byte SCB Support - SCSI CDB is embedded in the SCB to eliminate an + extra DMA.</li> + <li>Block Move Instruction Support - Doubles the speed of certain sequencer + operations.</li> + <li>‘Bayonet’ style Scatter Gather Engine - Improves S/G + prefetch performance.</li> + <li>Queuing Registers - Allows queueing of new transactions without pausing + the sequencer.</li> + <li>Multiple Target IDs - Allows the controller to respond to selection as a + target on multiple SCSI IDs.</li> +</ol> +</div> +</section> +<section class="Sh"> +<h1 class="Sh" id="CONFIGURATION_OPTIONS"><a class="permalink" href="#CONFIGURATION_OPTIONS">CONFIGURATION + OPTIONS</a></h1> +<p class="Pp">To allow PCI adapters to use memory mapped I/O if enabled:</p> +<p class="Pp"><code class="Cd">options AHC_ALLOW_MEMIO=(0 -- disabled, 1 -- + enabled)</code></p> +<div class="Bd Pp Bd-indent">Memory mapped I/O is more efficient than the + alternative, programmed I/O. Most PCI BIOSes will map devices so that either + technique for communicating with the card is available. In some cases, usually + when the PCI device is sitting behind a PCI->PCI bridge, the BIOS may fail + to properly initialize the chip for memory mapped I/O. The typical symptom of + this problem is a system hang if memory mapped I/O is attempted. +<p class="Pp">Most modern motherboards perform the initialization correctly and + work fine with this option enabled and it is the default. This option can + also be dynamically configured through a device hint documented below.</p> +</div> +<p class="Pp">To statically configure one or more controllers to assume the + target role:</p> +<p class="Pp"><code class="Cd">options AHC_TMODE_ENABLE=<bitmask of + units></code></p> +<div class="Bd Pp Bd-indent">The value assigned to this option should be a + bitmap of all units where target mode is desired. For example, a value of + 0x25, would enable target mode on units 0, 2, and 5. A value of 0x8a enables + it for units 1, 3, and 7. +<p class="Pp">Note that controllers can be dynamically configured through a + device hint documented below.</p> +</div> +</section> +<section class="Sh"> +<h1 class="Sh" id="BOOT_OPTIONS"><a class="permalink" href="#BOOT_OPTIONS">BOOT + OPTIONS</a></h1> +<p class="Pp">The following options are switchable by setting values in + <span class="Pa">/boot/device.hints</span>.</p> +<p class="Pp">They are:</p> +<dl class="Bl-tag"> + <dt id="hint.ahc."><var class="Va">hint.ahc.</var><var class="Ar">N</var><var class="Va">.tmode_enable</var></dt> + <dd>A hint to define whether the SCSI target mode is enabled, defaults to + disabled (0 -- disabled, 1 -- enabled).</dd> + <dt id="hint.ahc.~2"><var class="Va">hint.ahc.</var><var class="Ar">N</var><var class="Va">.allow_memio</var></dt> + <dd>A hint to define whether memory mapped io is enabled or disabled for this + adapter, defaults to enabled (0 -- disabled, 1 -- enabled).</dd> +</dl> +</section> +<section class="Sh"> +<h1 class="Sh" id="HARDWARE"><a class="permalink" href="#HARDWARE">HARDWARE</a></h1> +<p class="Pp">The <code class="Nm">ahc</code> driver supports the following + VL/ISA/PCI parallel SCSI controllers and cards:</p> +<p class="Pp"></p> +<ul class="Bl-bullet Bl-compact"> + <li>Adaptec AIC7770 host adapter chip</li> + <li>Adaptec AIC7850 host adapter chip</li> + <li>Adaptec AIC7860 host adapter chip</li> + <li>Adaptec AIC7870 host adapter chip</li> + <li>Adaptec AIC7880 host adapter chip</li> + <li>Adaptec AIC7890 host adapter chip</li> + <li>Adaptec AIC7891 host adapter chip</li> + <li>Adaptec AIC7892 host adapter chip</li> + <li>Adaptec AIC7895 host adapter chip</li> + <li>Adaptec AIC7896 host adapter chip</li> + <li>Adaptec AIC7897 host adapter chip</li> + <li>Adaptec AIC7899 host adapter chip</li> + <li>Adaptec 274X(W)</li> + <li>Adaptec 274X(T)</li> + <li>Adaptec 2910</li> + <li>Adaptec 2915</li> + <li>Adaptec 2920C</li> + <li>Adaptec 2930C</li> + <li>Adaptec 2930U2</li> + <li>Adaptec 2940</li> + <li>Adaptec 2940J</li> + <li>Adaptec 2940N</li> + <li>Adaptec 2940U</li> + <li>Adaptec 2940AU</li> + <li>Adaptec 2940UW</li> + <li>Adaptec 2940UW Dual</li> + <li>Adaptec 2940UW Pro</li> + <li>Adaptec 2940U2W</li> + <li>Adaptec 2940U2B</li> + <li>Adaptec 2950U2W</li> + <li>Adaptec 2950U2B</li> + <li>Adaptec 19160B</li> + <li>Adaptec 29160B</li> + <li>Adaptec 29160N</li> + <li>Adaptec 3940</li> + <li>Adaptec 3940U</li> + <li>Adaptec 3940AU</li> + <li>Adaptec 3940UW</li> + <li>Adaptec 3940AUW</li> + <li>Adaptec 3940U2W</li> + <li>Adaptec 3950U2</li> + <li>Adaptec 3960</li> + <li>Adaptec 39160</li> + <li>Adaptec 3985</li> + <li>Adaptec 4944UW</li> + <li>Many motherboards with on-board SCSI support</li> +</ul> +</section> +<section class="Sh"> +<h1 class="Sh" id="SCSI_CONTROL_BLOCKS_(SCBs)"><a class="permalink" href="#SCSI_CONTROL_BLOCKS_(SCBs)">SCSI + CONTROL BLOCKS (SCBs)</a></h1> +<p class="Pp">Every transaction sent to a device on the SCSI bus is assigned a + ‘SCSI Control Block’ (SCB). The SCB contains all of the + information required by the controller to process a transaction. The chip + feature table lists the number of SCBs that can be stored in on-chip memory. + All chips with model numbers greater than or equal to 7870 allow for the on + chip SCB space to be augmented with external SRAM up to a maximum of 255 + SCBs. Very few Adaptec controller configurations have external SRAM.</p> +<p class="Pp" id="SCB">If external SRAM is not available, SCBs are a limited + resource. Using the SCBs in a straight forward manner would only allow the + driver to handle as many concurrent transactions as there are physical SCBs. + To fully utilize the SCSI bus and the devices on it, requires much more + concurrency. The solution to this problem is + <a class="permalink" href="#SCB"><i class="Em">SCB Paging</i></a>, a concept + similar to memory paging. SCB paging takes advantage of the fact that + devices usually disconnect from the SCSI bus for long periods of time + without talking to the controller. The SCBs for disconnected transactions + are only of use to the controller when the transfer is resumed. When the + host queues another transaction for the controller to execute, the + controller firmware will use a free SCB if one is available. Otherwise, the + state of the most recently disconnected (and therefore most likely to stay + disconnected) SCB is saved, via dma, to host memory, and the local SCB + reused to start the new transaction. This allows the controller to queue up + to 255 transactions regardless of the amount of SCB space. Since the local + SCB space serves as a cache for disconnected transactions, the more SCB + space available, the less host bus traffic consumed saving and restoring SCB + data.</p> +</section> +<section class="Sh"> +<h1 class="Sh" id="SEE_ALSO"><a class="permalink" href="#SEE_ALSO">SEE + ALSO</a></h1> +<p class="Pp"><a class="Xr">ahd(4)</a>, <a class="Xr">cd(4)</a>, + <a class="Xr">da(4)</a>, <a class="Xr">sa(4)</a>, + <a class="Xr">scsi(4)</a></p> +</section> +<section class="Sh"> +<h1 class="Sh" id="HISTORY"><a class="permalink" href="#HISTORY">HISTORY</a></h1> +<p class="Pp">The <code class="Nm">ahc</code> driver appeared in + <span class="Ux">FreeBSD 2.0</span>.</p> +</section> +<section class="Sh"> +<h1 class="Sh" id="AUTHORS"><a class="permalink" href="#AUTHORS">AUTHORS</a></h1> +<p class="Pp">The <code class="Nm">ahc</code> driver, the AIC7xxx sequencer-code + assembler, and the firmware running on the aic7xxx chips was written by + <span class="An">Justin T. Gibbs</span>.</p> +</section> +<section class="Sh"> +<h1 class="Sh" id="BUGS"><a class="permalink" href="#BUGS">BUGS</a></h1> +<p class="Pp">Some Quantum drives (at least the Empire 2100 and 1080s) will not + run on an AIC7870 Rev B in synchronous mode at 10MHz. Controllers with this + problem have a 42 MHz clock crystal on them and run slightly above 10MHz. + This confuses the drive and hangs the bus. Setting a maximum synchronous + negotiation rate of 8MHz in the SCSI-Select utility will allow normal + operation.</p> +<p class="Pp">Although the Ultra2 and Ultra160 products have sufficient + instruction ram space to support both the initiator and target roles + concurrently, this configuration is disabled in favor of allowing the target + role to respond on multiple target ids. A method for configuring dual role + mode should be provided.</p> +<p class="Pp">Tagged Queuing is not supported in target mode.</p> +<p class="Pp">Reselection in target mode fails to function correctly on all high + voltage differential boards as shipped by Adaptec. Information on how to + modify HVD board to work correctly in target mode is available from + Adaptec.</p> +</section> +</div> +<table class="foot"> + <tr> + <td class="foot-date">September 29, 2025</td> + <td class="foot-os">FreeBSD 15.0</td> + </tr> +</table> |