From 2999bd3b9466617938f2f7ceb689cfbe33b46cd9 Mon Sep 17 00:00:00 2001
From: Jacob McDonnell <jacob@jacobmcdonnell.com>
Date: Sun, 15 Mar 2026 21:51:55 -0400
Subject: feat: Initial mapping of registers and instructions

Mapping of registers from register names to numbers. As well, the inital
mapping of instructions to their opcodes has been added. There are bit
fields for each type of instruction, and a tagged union of all the
instruction types.
---
 src/asm.cpp | 143 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 src/asm.hpp |  74 +++++++++++++++++++++++++++++++
 2 files changed, 217 insertions(+)
 create mode 100644 src/asm.cpp
 create mode 100644 src/asm.hpp

diff --git a/src/asm.cpp b/src/asm.cpp
new file mode 100644
index 0000000..d79f086
--- /dev/null
+++ b/src/asm.cpp
@@ -0,0 +1,143 @@
+#include <cstdint>
+#include <map>
+#include <string>
+#include "asm.hpp"
+
+namespace {
+std::map<std::string, instruction_t> instructions = {
+    {"lb", {}},
+    {"lh", {}},
+    {"lw", {}},
+    {"ld", {}},
+    {"lbu", {}},
+    {"lhu", {}},
+    {"lwu", {}},
+    {"sb", {}},
+    {"sh", {}},
+    {"sw", {}},
+    {"sd", {}},
+    {"li", {}},
+    {"lui", {}},
+    {"auipc", {}},
+    {"mv", {}},
+    {"sext.b", {}},
+    {"sext.h", {}},
+    {"sext.w", {}},
+    {"zext.b", {}},
+    {"zext.h", {}},
+    {"zext.w", {}},
+    {"rev8", {}},
+    {"czero.eqz", {}},
+    {"czero.nez", {}},
+    {"addi", {}},
+    {"add", {}},
+    {"sh1add", {}},
+    {"sh2add", {}},
+    {"sh3add", {}},
+    {"add.wu", {}},
+    {"sh1add.wu", {}},
+    {"sh2add.wu", {}},
+    {"sh3add.wu", {}},
+    {"addiw", {}},
+    {"addw", {}},
+    {"sub", {}},
+    {"subw", {}},
+    {"neg", {}},
+    {"negw", {}},
+    {"mul", {}},
+    {"mulw", {}},
+    {"mulh", {}},
+    {"mulhu", {}},
+    {"mulhsu", {}},
+    {"div", {}},
+    {"divu", {}},
+    {"rem", {}},
+    {"remu", {}},
+    {"min", {}},
+    {"max", {}},
+    {"minu", {}},
+    {"maxu", {}},
+    {"seqz", {}},
+    {"snez", {}},
+    {"slti", {}},
+    {"slt", {}},
+    {"sltiu", {}},
+    {"sltu", {}},
+    {"bexti", {}},
+    {"bext", {}},
+    {"andi", {}},
+    {"and", {}},
+    {"andn", {}},
+    {"bclri", {}},
+    {"bclr", {}},
+    {"ori", {}},
+    {"or", {}},
+    {"orn", {}},
+    {"bseti", {}},
+    {"bset", {}},
+    {"xori", {}},
+    {"xor", {}},
+    {"xnor", {}},
+    {"binvi", {}},
+    {"binv", {}},
+    {"not", {}},
+    {"orc.b", {}},
+    {"slli", {}},
+    {"sll", {}},
+    {"slliw", {}},
+    {"sllw", {}},
+    {"slli.wu", {}},
+    {"srli", {}},
+    {"srl", {}},
+    {"srliw", {}},
+    {"srlw", {}},
+    {"srai", {}},
+    {"sra", {}},
+    {"sraiw", {}},
+    {"sraw", {}},
+    {"rori", {}},
+    {"ror", {}},
+    {"rol", {}},
+    {"roriw", {}},
+    {"rorw", {}},
+    {"rolw", {}},
+    {"clz", {}},
+    {"clzw", {}},
+    {"ctz", {}},
+    {"ctzw", {}},
+    {"cpop", {}},
+    {"cpopw", {}},
+    {"j", {}},
+    {"jal", {}},
+    {"jr", {}},
+    {"jalr", {}},
+    {"call", {}},
+    {"tail", {}},
+    {"ret", {}},
+    {"beq", {}},
+    {"bne", {}},
+    {"blt", {}},
+    {"bgt", {}},
+    {"bge", {}},
+    {"ble", {}},
+    {"bltu", {}},
+    {"bgtu", {}},
+    {"bgeu", {}},
+    {"bleu", {}},
+    {"nop", {}},
+    {"ecall", {}},
+    {"ebreak", {}},
+};
+
+std::map<std::string, uint8_t> registers = {
+    {"x0", 0},   {"x1", 1},   {"x2", 2},   {"x3", 3},   {"x4", 4},   {"x5", 5},   {"x6", 6},   {"x7", 7},   {"x8", 8},
+    {"x9", 9},   {"x10", 10}, {"x11", 11}, {"x12", 12}, {"x13", 13}, {"x14", 14}, {"x15", 15}, {"x16", 16}, {"x17", 17},
+    {"x18", 18}, {"x19", 19}, {"x20", 20}, {"x21", 21}, {"x22", 22}, {"x23", 23}, {"x24", 24}, {"x25", 25}, {"x26", 26},
+    {"x27", 27}, {"x28", 28}, {"x29", 29}, {"x30", 30}, {"x31", 31}, {"zero", 0}, {"ra", 1},   {"sp", 2},   {"gp", 3},
+    {"tp", 4},   {"t0", 5},   {"t1", 6},   {"t2", 7},   {"s0", 8},   {"fp", 8},   {"s1", 9},   {"a0", 10},  {"a1", 11},
+    {"a2", 12},  {"a3", 13},  {"a4", 14},  {"a5", 15},  {"a6", 16},  {"a7", 17},  {"s2", 18},  {"s3", 19},  {"s4", 20},
+    {"s5", 21},  {"s6", 22},  {"s7", 23},  {"s8", 24},  {"s9", 25},  {"s10", 26}, {"s11", 27}, {"t3", 28},  {"t4", 29},
+    {"t5", 30},  {"t6", 31},
+};
+} // namespace
+
diff --git a/src/asm.hpp b/src/asm.hpp
new file mode 100644
index 0000000..4d5eb73
--- /dev/null
+++ b/src/asm.hpp
@@ -0,0 +1,74 @@
+#ifndef SRC_ASM_HPP_
+#define SRC_ASM_HPP_
+
+#include <cstdint>
+
+enum class type_t {R, I, S, U, B, J};
+
+struct r_type {
+    uint32_t funct7 : 7;
+    uint32_t rs2    : 5;
+    uint32_t rs1    : 5;
+    uint32_t funct3 : 3;
+    uint32_t rd     : 5;
+    uint32_t opcode : 7;
+};
+
+struct i_type {
+    uint32_t imm    : 12;
+    uint32_t rs1    : 5;
+    uint32_t funct3 : 3;
+    uint32_t rd     : 5;
+    uint32_t opcode : 7;
+};
+
+struct s_type {
+    uint32_t imm_hi : 7;
+    uint32_t rs2    : 5;
+    uint32_t rs1    : 5;
+    uint32_t funct3 : 3;
+    uint32_t imm_lo : 5;
+    uint32_t opcode : 7;
+};
+
+struct u_type {
+    uint32_t imm    : 10;
+    uint32_t rd     : 5;
+    uint32_t opcode : 7;
+};
+
+struct b_type {
+    uint32_t a      : 1;
+    uint32_t imm_hi : 6;
+    uint32_t rs2    : 5;
+    uint32_t rs1    : 5;
+    uint32_t funct3 : 3;
+    uint32_t imm_lo : 4;
+    uint32_t b      : 1;
+    uint32_t opcode : 7;
+};
+
+struct j_type {
+    uint32_t a      : 1;
+    uint32_t imm_lo : 10;
+    uint32_t b      : 1;
+    uint32_t imm_hi : 8;
+    uint32_t rd     : 5;
+    uint32_t opcode : 7;
+};
+
+struct instruction_t {
+    type_t t;
+    union {
+        r_type   r;
+        i_type   i;
+        s_type   s;
+        u_type   u;
+        b_type   b;
+        j_type   j;
+        uint32_t value;
+    };
+};
+
+#endif  // SRC_ASM_HPP_
+
-- 
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